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MIPS: Lantiq: Add support for setting PMU register on AR10 and GRX390
This adds support for setting the PMU register on the AR10 and GRX390. Signed-off-by: Hauke Mehrtens <hauke.mehrtens@lantiq.com> Acked-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/11382/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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1 changed files with 73 additions and 11 deletions
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@ -10,6 +10,7 @@
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#include <linux/ioport.h>
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#include <linux/export.h>
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#include <linux/clkdev.h>
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#include <linux/spinlock.h>
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#include <linux/of.h>
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#include <linux/of_platform.h>
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#include <linux/of_address.h>
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@ -19,16 +20,18 @@
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#include "../clk.h"
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#include "../prom.h"
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/* clock control register */
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/* clock control register for legacy */
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#define CGU_IFCCR 0x0018
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#define CGU_IFCCR_VR9 0x0024
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/* system clock register */
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/* system clock register for legacy */
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#define CGU_SYS 0x0010
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/* pci control register */
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#define CGU_PCICR 0x0034
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#define CGU_PCICR_VR9 0x0038
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/* ephy configuration register */
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#define CGU_EPHY 0x10
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/* Legacy PMU register for ar9, ase, danube */
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/* power control register */
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#define PMU_PWDCR 0x1C
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/* power status register */
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@ -42,6 +45,47 @@
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/* power status register */
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#define PWDSR(x) ((x) ? (PMU_PWDSR1) : (PMU_PWDSR))
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/* PMU register for ar10 and grx390 */
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/* First register set */
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#define PMU_CLK_SR 0x20 /* status */
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#define PMU_CLK_CR_A 0x24 /* Enable */
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#define PMU_CLK_CR_B 0x28 /* Disable */
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/* Second register set */
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#define PMU_CLK_SR1 0x30 /* status */
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#define PMU_CLK_CR1_A 0x34 /* Enable */
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#define PMU_CLK_CR1_B 0x38 /* Disable */
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/* Third register set */
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#define PMU_ANA_SR 0x40 /* status */
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#define PMU_ANA_CR_A 0x44 /* Enable */
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#define PMU_ANA_CR_B 0x48 /* Disable */
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/* Status */
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static u32 pmu_clk_sr[] = {
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PMU_CLK_SR,
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PMU_CLK_SR1,
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PMU_ANA_SR,
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};
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/* Enable */
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static u32 pmu_clk_cr_a[] = {
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PMU_CLK_CR_A,
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PMU_CLK_CR1_A,
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PMU_ANA_CR_A,
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};
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/* Disable */
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static u32 pmu_clk_cr_b[] = {
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PMU_CLK_CR_B,
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PMU_CLK_CR1_B,
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PMU_ANA_CR_B,
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};
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#define PWDCR_EN_XRX(x) (pmu_clk_cr_a[(x)])
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#define PWDCR_DIS_XRX(x) (pmu_clk_cr_b[(x)])
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#define PWDSR_XRX(x) (pmu_clk_sr[(x)])
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/* clock gates that we can en/disable */
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#define PMU_USB0_P BIT(0)
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#define PMU_PCI BIT(4)
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@ -136,11 +180,20 @@ static int pmu_enable(struct clk *clk)
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{
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int retry = 1000000;
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spin_lock(&g_pmu_lock);
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pmu_w32(pmu_r32(PWDCR(clk->module)) & ~clk->bits,
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PWDCR(clk->module));
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do {} while (--retry && (pmu_r32(PWDSR(clk->module)) & clk->bits));
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spin_unlock(&g_pmu_lock);
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if (of_machine_is_compatible("lantiq,ar10")
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|| of_machine_is_compatible("lantiq,grx390")) {
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pmu_w32(clk->bits, PWDCR_EN_XRX(clk->module));
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do {} while (--retry &&
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(!(pmu_r32(PWDSR_XRX(clk->module)) & clk->bits)));
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} else {
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spin_lock(&g_pmu_lock);
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pmu_w32(pmu_r32(PWDCR(clk->module)) & ~clk->bits,
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PWDCR(clk->module));
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do {} while (--retry &&
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(pmu_r32(PWDSR(clk->module)) & clk->bits));
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spin_unlock(&g_pmu_lock);
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}
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if (!retry)
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panic("activating PMU module failed!");
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@ -153,10 +206,19 @@ static void pmu_disable(struct clk *clk)
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{
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int retry = 1000000;
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spin_lock(&g_pmu_lock);
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pmu_w32(pmu_r32(PWDCR(clk->module)) | clk->bits, PWDCR(clk->module));
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do {} while (--retry && (!(pmu_r32(PWDSR(clk->module)) & clk->bits)));
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spin_unlock(&g_pmu_lock);
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if (of_machine_is_compatible("lantiq,ar10")
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|| of_machine_is_compatible("lantiq,grx390")) {
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pmu_w32(clk->bits, PWDCR_DIS_XRX(clk->module));
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do {} while (--retry &&
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(pmu_r32(PWDSR_XRX(clk->module)) & clk->bits));
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} else {
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spin_lock(&g_pmu_lock);
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pmu_w32(pmu_r32(PWDCR(clk->module)) | clk->bits,
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PWDCR(clk->module));
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do {} while (--retry &&
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(!(pmu_r32(PWDSR(clk->module)) & clk->bits)));
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spin_unlock(&g_pmu_lock);
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}
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if (!retry)
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pr_warn("deactivating PMU module failed!");
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