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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-09-29 22:02:02 +00:00
Merge remote-tracking branch 'spi/for-5.20' into spi-6.0
This commit is contained in:
Mark Brown
commit
75c971dd6c
6 changed files with 112 additions and 39 deletions
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@ -10,7 +10,7 @@ description:
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See spi-peripheral-props.yaml for more info.
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maintainers:
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- Pratyush Yadav <p.yadav@ti.com>
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- Vaishnav Achath <vaishnav.a@ti.com>
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properties:
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# cdns,qspi-nor.yaml
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@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Cadence Quad SPI controller
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maintainers:
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- Pratyush Yadav <p.yadav@ti.com>
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- Vaishnav Achath <vaishnav.a@ti.com>
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allOf:
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- $ref: spi-controller.yaml#
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@ -16,7 +16,7 @@ description:
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their own separate schema that should be referenced from here.
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maintainers:
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- Pratyush Yadav <p.yadav@ti.com>
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- Mark Brown <broonie@kernel.org>
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properties:
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reg:
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@ -2178,7 +2178,7 @@ M: Jean-Marie Verdun <verdun@hpe.com>
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M: Nick Hawkins <nick.hawkins@hpe.com>
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S: Maintained
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F: Documentation/devicetree/bindings/arm/hpe,gxp.yaml
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F: Documentation/devicetree/bindings/spi/hpe,gxp-spi.yaml
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F: Documentation/devicetree/bindings/spi/hpe,gxp-spifi.yaml
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F: Documentation/devicetree/bindings/timer/hpe,gxp-timer.yaml
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F: arch/arm/boot/dts/hpe-bmc*
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F: arch/arm/boot/dts/hpe-gxp*
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@ -156,6 +156,7 @@ struct meson_spicc_device {
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void __iomem *base;
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struct clk *core;
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struct clk *pclk;
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struct clk_divider pow2_div;
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struct clk *clk;
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struct spi_message *message;
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struct spi_transfer *xfer;
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@ -168,6 +169,8 @@ struct meson_spicc_device {
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unsigned long xfer_remain;
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};
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#define pow2_clk_to_spicc(_div) container_of(_div, struct meson_spicc_device, pow2_div)
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static void meson_spicc_oen_enable(struct meson_spicc_device *spicc)
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{
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u32 conf;
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@ -421,7 +424,7 @@ static int meson_spicc_prepare_message(struct spi_master *master,
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{
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struct meson_spicc_device *spicc = spi_master_get_devdata(master);
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struct spi_device *spi = message->spi;
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u32 conf = 0;
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u32 conf = readl_relaxed(spicc->base + SPICC_CONREG) & SPICC_DATARATE_MASK;
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/* Store current message */
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spicc->message = message;
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@ -458,8 +461,6 @@ static int meson_spicc_prepare_message(struct spi_master *master,
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/* Select CS */
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conf |= FIELD_PREP(SPICC_CS_MASK, spi->chip_select);
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/* Default Clock rate core/4 */
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/* Default 8bit word */
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conf |= FIELD_PREP(SPICC_BITLENGTH_MASK, 8 - 1);
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@ -476,12 +477,16 @@ static int meson_spicc_prepare_message(struct spi_master *master,
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static int meson_spicc_unprepare_transfer(struct spi_master *master)
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{
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struct meson_spicc_device *spicc = spi_master_get_devdata(master);
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u32 conf = readl_relaxed(spicc->base + SPICC_CONREG) & SPICC_DATARATE_MASK;
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/* Disable all IRQs */
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writel(0, spicc->base + SPICC_INTREG);
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device_reset_optional(&spicc->pdev->dev);
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/* Set default configuration, keeping datarate field */
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writel_relaxed(conf, spicc->base + SPICC_CONREG);
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return 0;
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}
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@ -518,14 +523,60 @@ static void meson_spicc_cleanup(struct spi_device *spi)
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* Clk path for G12A series:
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* pclk -> pow2 fixed div -> pow2 div -> mux -> out
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* pclk -> enh fixed div -> enh div -> mux -> out
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*
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* The pow2 divider is tied to the controller HW state, and the
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* divider is only valid when the controller is initialized.
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*
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* A set of clock ops is added to make sure we don't read/set this
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* clock rate while the controller is in an unknown state.
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*/
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static int meson_spicc_clk_init(struct meson_spicc_device *spicc)
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static unsigned long meson_spicc_pow2_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk_divider *divider = to_clk_divider(hw);
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struct meson_spicc_device *spicc = pow2_clk_to_spicc(divider);
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if (!spicc->master->cur_msg || !spicc->master->busy)
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return 0;
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return clk_divider_ops.recalc_rate(hw, parent_rate);
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}
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static int meson_spicc_pow2_determine_rate(struct clk_hw *hw,
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struct clk_rate_request *req)
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{
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struct clk_divider *divider = to_clk_divider(hw);
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struct meson_spicc_device *spicc = pow2_clk_to_spicc(divider);
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if (!spicc->master->cur_msg || !spicc->master->busy)
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return -EINVAL;
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return clk_divider_ops.determine_rate(hw, req);
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}
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static int meson_spicc_pow2_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct clk_divider *divider = to_clk_divider(hw);
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struct meson_spicc_device *spicc = pow2_clk_to_spicc(divider);
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if (!spicc->master->cur_msg || !spicc->master->busy)
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return -EINVAL;
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return clk_divider_ops.set_rate(hw, rate, parent_rate);
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}
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const struct clk_ops meson_spicc_pow2_clk_ops = {
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.recalc_rate = meson_spicc_pow2_recalc_rate,
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.determine_rate = meson_spicc_pow2_determine_rate,
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.set_rate = meson_spicc_pow2_set_rate,
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};
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static int meson_spicc_pow2_clk_init(struct meson_spicc_device *spicc)
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{
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struct device *dev = &spicc->pdev->dev;
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struct clk_fixed_factor *pow2_fixed_div, *enh_fixed_div;
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struct clk_divider *pow2_div, *enh_div;
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struct clk_mux *mux;
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struct clk_fixed_factor *pow2_fixed_div;
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struct clk_init_data init;
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struct clk *clk;
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struct clk_parent_data parent_data[2];
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@ -560,31 +611,45 @@ static int meson_spicc_clk_init(struct meson_spicc_device *spicc)
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if (WARN_ON(IS_ERR(clk)))
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return PTR_ERR(clk);
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pow2_div = devm_kzalloc(dev, sizeof(*pow2_div), GFP_KERNEL);
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if (!pow2_div)
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return -ENOMEM;
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snprintf(name, sizeof(name), "%s#pow2_div", dev_name(dev));
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init.name = name;
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init.ops = &clk_divider_ops;
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init.flags = CLK_SET_RATE_PARENT;
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init.ops = &meson_spicc_pow2_clk_ops;
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/*
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* Set NOCACHE here to make sure we read the actual HW value
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* since we reset the HW after each transfer.
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*/
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init.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE;
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parent_data[0].hw = &pow2_fixed_div->hw;
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init.num_parents = 1;
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pow2_div->shift = 16,
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pow2_div->width = 3,
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pow2_div->flags = CLK_DIVIDER_POWER_OF_TWO,
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pow2_div->reg = spicc->base + SPICC_CONREG;
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pow2_div->hw.init = &init;
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spicc->pow2_div.shift = 16,
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spicc->pow2_div.width = 3,
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spicc->pow2_div.flags = CLK_DIVIDER_POWER_OF_TWO,
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spicc->pow2_div.reg = spicc->base + SPICC_CONREG;
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spicc->pow2_div.hw.init = &init;
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clk = devm_clk_register(dev, &pow2_div->hw);
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if (WARN_ON(IS_ERR(clk)))
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return PTR_ERR(clk);
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spicc->clk = devm_clk_register(dev, &spicc->pow2_div.hw);
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if (WARN_ON(IS_ERR(spicc->clk)))
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return PTR_ERR(spicc->clk);
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if (!spicc->data->has_enhance_clk_div) {
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spicc->clk = clk;
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return 0;
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}
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return 0;
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}
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static int meson_spicc_enh_clk_init(struct meson_spicc_device *spicc)
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{
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struct device *dev = &spicc->pdev->dev;
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struct clk_fixed_factor *enh_fixed_div;
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struct clk_divider *enh_div;
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struct clk_mux *mux;
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struct clk_init_data init;
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struct clk *clk;
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struct clk_parent_data parent_data[2];
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char name[64];
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memset(&init, 0, sizeof(init));
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memset(&parent_data, 0, sizeof(parent_data));
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init.parent_data = parent_data;
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/* algorithm for enh div: rate = freq / 2 / (N + 1) */
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@ -637,7 +702,7 @@ static int meson_spicc_clk_init(struct meson_spicc_device *spicc)
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snprintf(name, sizeof(name), "%s#sel", dev_name(dev));
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init.name = name;
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init.ops = &clk_mux_ops;
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parent_data[0].hw = &pow2_div->hw;
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parent_data[0].hw = &spicc->pow2_div.hw;
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parent_data[1].hw = &enh_div->hw;
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init.num_parents = 2;
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init.flags = CLK_SET_RATE_PARENT;
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@ -754,12 +819,20 @@ static int meson_spicc_probe(struct platform_device *pdev)
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meson_spicc_oen_enable(spicc);
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ret = meson_spicc_clk_init(spicc);
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ret = meson_spicc_pow2_clk_init(spicc);
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if (ret) {
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dev_err(&pdev->dev, "clock registration failed\n");
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dev_err(&pdev->dev, "pow2 clock registration failed\n");
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goto out_clk;
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}
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if (spicc->data->has_enhance_clk_div) {
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ret = meson_spicc_enh_clk_init(spicc);
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if (ret) {
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dev_err(&pdev->dev, "clock registration failed\n");
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goto out_clk;
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}
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}
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ret = devm_spi_register_master(&pdev->dev, master);
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if (ret) {
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dev_err(&pdev->dev, "spi master registration failed\n");
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@ -95,7 +95,7 @@ static ssize_t driver_override_show(struct device *dev,
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}
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static DEVICE_ATTR_RW(driver_override);
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static struct spi_statistics *spi_alloc_pcpu_stats(struct device *dev)
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static struct spi_statistics __percpu *spi_alloc_pcpu_stats(struct device *dev)
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{
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struct spi_statistics __percpu *pcpu_stats;
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@ -162,7 +162,7 @@ static struct device_attribute dev_attr_spi_device_##field = { \
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}
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#define SPI_STATISTICS_SHOW_NAME(name, file, field) \
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static ssize_t spi_statistics_##name##_show(struct spi_statistics *stat, \
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static ssize_t spi_statistics_##name##_show(struct spi_statistics __percpu *stat, \
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char *buf) \
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{ \
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ssize_t len; \
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@ -309,7 +309,7 @@ static const struct attribute_group *spi_master_groups[] = {
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NULL,
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};
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static void spi_statistics_add_transfer_stats(struct spi_statistics *pcpu_stats,
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static void spi_statistics_add_transfer_stats(struct spi_statistics __percpu *pcpu_stats,
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struct spi_transfer *xfer,
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struct spi_controller *ctlr)
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{
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@ -1275,8 +1275,8 @@ static int spi_transfer_wait(struct spi_controller *ctlr,
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struct spi_message *msg,
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struct spi_transfer *xfer)
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{
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struct spi_statistics *statm = ctlr->pcpu_statistics;
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struct spi_statistics *stats = msg->spi->pcpu_statistics;
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struct spi_statistics __percpu *statm = ctlr->pcpu_statistics;
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struct spi_statistics __percpu *stats = msg->spi->pcpu_statistics;
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u32 speed_hz = xfer->speed_hz;
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unsigned long long ms;
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@ -1432,8 +1432,8 @@ static int spi_transfer_one_message(struct spi_controller *ctlr,
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struct spi_transfer *xfer;
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bool keep_cs = false;
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int ret = 0;
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struct spi_statistics *statm = ctlr->pcpu_statistics;
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struct spi_statistics *stats = msg->spi->pcpu_statistics;
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struct spi_statistics __percpu *statm = ctlr->pcpu_statistics;
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struct spi_statistics __percpu *stats = msg->spi->pcpu_statistics;
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spi_set_cs(msg->spi, true, false);
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