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dt-bindings: riscv: Update DT binding docs to support SiFive FU740 SoC

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Add new compatible strings in cpus.yaml to support the E71 and U74 CPU
cores ("harts") that are present on FU740-C000 SoC.

Signed-off-by: Yash Shah <yash.shah@sifive.com>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
This commit is contained in:
Yash Shah 2020-12-08 10:25:33 +05:30 committed by Palmer Dabbelt
parent 507308b8cc
commit 75e6d7248e
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1 changed files with 6 additions and 0 deletions
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6
Documentation/devicetree/bindings/riscv/cpus.yaml
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@ -28,11 +28,17 @@ properties:
- items:
- enum:
- sifive,rocket0
- sifive,bullet0
- sifive,e5
- sifive,e7
- sifive,e51
- sifive,e71
- sifive,u54-mc
- sifive,u74-mc
- sifive,u54
- sifive,u74
- sifive,u5
- sifive,u7
- const: riscv
- const: riscv # Simulator only
description: