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OMAP2/3 SDRC: don't set SDRC_POWER.PWDENA on boot
Stop setting SDRC_POWER.PWDENA on boot. There is a nasty erratum (34xx erratum 1.150) that can cause memory corruption if PWDENA is enabled. Based originally on a patch from Samu P. Onkalo <samu.p.onkalo@nokia.com>. Tested on BeagleBoard rev C2. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Samu P. Onkalo <samu.p.onkalo@nokia.com>
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2 changed files with 4 additions and 3 deletions
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@ -125,8 +125,11 @@ void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
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sdrc_init_params_cs1 = sdrc_cs1;
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sdrc_init_params_cs1 = sdrc_cs1;
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/* XXX Enable SRFRONIDLEREQ here also? */
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/* XXX Enable SRFRONIDLEREQ here also? */
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/*
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* PWDENA should not be set due to 34xx erratum 1.150 - PWDENA
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* can cause random memory corruption
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*/
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l = (1 << SDRC_POWER_EXTCLKDIS_SHIFT) |
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l = (1 << SDRC_POWER_EXTCLKDIS_SHIFT) |
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(1 << SDRC_POWER_PWDENA_SHIFT) |
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(1 << SDRC_POWER_PAGEPOLICY_SHIFT);
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(1 << SDRC_POWER_PAGEPOLICY_SHIFT);
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sdrc_write_reg(l, SDRC_POWER);
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sdrc_write_reg(l, SDRC_POWER);
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}
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}
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@ -58,7 +58,6 @@
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/* SDRC_POWER bit settings */
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/* SDRC_POWER bit settings */
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#define SRFRONIDLEREQ_MASK 0x40
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#define SRFRONIDLEREQ_MASK 0x40
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#define PWDENA_MASK 0x4
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/* CM_IDLEST1_CORE bit settings */
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/* CM_IDLEST1_CORE bit settings */
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#define ST_SDRC_MASK 0x2
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#define ST_SDRC_MASK 0x2
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@ -160,7 +159,6 @@ sdram_in_selfrefresh:
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ldr r12, [r11] @ read the contents of SDRC_POWER
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ldr r12, [r11] @ read the contents of SDRC_POWER
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mov r9, r12 @ keep a copy of SDRC_POWER bits
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mov r9, r12 @ keep a copy of SDRC_POWER bits
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orr r12, r12, #SRFRONIDLEREQ_MASK @ enable self refresh on idle
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orr r12, r12, #SRFRONIDLEREQ_MASK @ enable self refresh on idle
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bic r12, r12, #PWDENA_MASK @ clear PWDENA
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str r12, [r11] @ write back to SDRC_POWER register
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str r12, [r11] @ write back to SDRC_POWER register
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ldr r12, [r11] @ posted-write barrier for SDRC
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ldr r12, [r11] @ posted-write barrier for SDRC
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idle_sdrc:
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idle_sdrc:
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