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perf/x86/intel/pebs: Robustify PEBS buffer drain
Vince Weaver and Stephane Eranian reported warnings in the PEBS code when running the perf fuzzer. Stephane wrote: > I can reproduce the problem on my HSW running the fuzzer. > > I can see why this could be happening if you are mixing PEBS and non PEBS events > in the bottom 4 counters. I suspect: > for (bit = 0; bit < x86_pmu.max_pebs_events; bit++) { > if ((counts[bit] == 0) && (error[bit] == 0)) > continue; > > This test is not correct when you have non-PEBS events mixed with > PEBS events and they overflow at the same time. They will have > counts[i] != 0 but error[i] == 0, and thus you fall thru the loop > and hit the assert. Or it is something along those lines. The only way I can make this work is if ->status only has !PEBS events set, because if it has both set we'll take that slow path which masks out the !PEBS bits. After masking there are 3 options: - there is one bit set, and its @bit, we increment counts[bit]. - there are multiple bits set, we increment error[] for each set bit, we do not increment counts[]. - there are no bits set, we do nothing. The intent was to never increment counts[] for !PEBS events. Now if we start out with only a single !PEBS event set, we'll pass the test and increment counts[] for a !PEBS and hit the warn. Reported-by: Vince Weaver <vincent.weaver@maine.edu> Reported-by: Stephane Eranian <eranian@google.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: Arnaldo Carvalho de Melo <acme@kernel.org> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: kan.liang@intel.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
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1 changed files with 17 additions and 17 deletions
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@ -1188,6 +1188,7 @@ static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs)
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for (at = base; at < top; at += x86_pmu.pebs_record_size) {
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for (at = base; at < top; at += x86_pmu.pebs_record_size) {
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struct pebs_record_nhm *p = at;
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struct pebs_record_nhm *p = at;
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u64 pebs_status;
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/* PEBS v3 has accurate status bits */
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/* PEBS v3 has accurate status bits */
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if (x86_pmu.intel_cap.pebs_format >= 3) {
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if (x86_pmu.intel_cap.pebs_format >= 3) {
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@ -1198,12 +1199,17 @@ static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs)
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continue;
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continue;
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}
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}
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bit = find_first_bit((unsigned long *)&p->status,
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pebs_status = p->status & cpuc->pebs_enabled;
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pebs_status &= (1ULL << x86_pmu.max_pebs_events) - 1;
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bit = find_first_bit((unsigned long *)&pebs_status,
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x86_pmu.max_pebs_events);
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x86_pmu.max_pebs_events);
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if (bit >= x86_pmu.max_pebs_events)
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if (WARN(bit >= x86_pmu.max_pebs_events,
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continue;
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"PEBS record without PEBS event! status=%Lx pebs_enabled=%Lx active_mask=%Lx",
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if (!test_bit(bit, cpuc->active_mask))
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(unsigned long long)p->status, (unsigned long long)cpuc->pebs_enabled,
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*(unsigned long long *)cpuc->active_mask))
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continue;
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continue;
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/*
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/*
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* The PEBS hardware does not deal well with the situation
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* The PEBS hardware does not deal well with the situation
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* when events happen near to each other and multiple bits
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* when events happen near to each other and multiple bits
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@ -1218,27 +1224,21 @@ static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs)
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* one, and it's not possible to reconstruct all events
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* one, and it's not possible to reconstruct all events
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* that caused the PEBS record. It's called collision.
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* that caused the PEBS record. It's called collision.
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* If collision happened, the record will be dropped.
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* If collision happened, the record will be dropped.
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*
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*/
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*/
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if (p->status != (1 << bit)) {
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if (p->status != (1ULL << bit)) {
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u64 pebs_status;
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for_each_set_bit(i, (unsigned long *)&pebs_status,
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x86_pmu.max_pebs_events)
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/* slow path */
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error[i]++;
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pebs_status = p->status & cpuc->pebs_enabled;
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continue;
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pebs_status &= (1ULL << MAX_PEBS_EVENTS) - 1;
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if (pebs_status != (1 << bit)) {
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for_each_set_bit(i, (unsigned long *)&pebs_status,
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MAX_PEBS_EVENTS)
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error[i]++;
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continue;
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}
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}
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}
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counts[bit]++;
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counts[bit]++;
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}
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}
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for (bit = 0; bit < x86_pmu.max_pebs_events; bit++) {
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for (bit = 0; bit < x86_pmu.max_pebs_events; bit++) {
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if ((counts[bit] == 0) && (error[bit] == 0))
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if ((counts[bit] == 0) && (error[bit] == 0))
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continue;
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continue;
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event = cpuc->events[bit];
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event = cpuc->events[bit];
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WARN_ON_ONCE(!event);
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WARN_ON_ONCE(!event);
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WARN_ON_ONCE(!event->attr.precise_ip);
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WARN_ON_ONCE(!event->attr.precise_ip);
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