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drm/msm/dpu: separate DSC flush update out of interface
Currently DSC flushing happens during interface configuration at dpu_hw_ctl_intf_cfg_v1(). Separate DSC flush away from dpu_hw_ctl_intf_cfg_v1() by adding dpu_hw_ctl_update_pending_flush_dsc_v1() to handle both per-DSC engine and DSC flush bits at same time to make it consistent with the location of flush programming of other DPU sub-blocks. Changes in v10: -- rewording commit text -- pass ctl directly instead of dpu_enc to dsc_pipe_cfg() -- ctx->pending_dsc_flush_mask = 0; Changes in v11: -- add Fixes tag Changes in v12: -- move dsc parameter to next line at dpu_encoder_dsc_pipe_cfg() Changes in v14: -- Fixes tag had been move to 1st patch of this series Signed-off-by: Kuogee Hsieh <quic_khsieh@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> Patchwork: https://patchwork.freedesktop.org/patch/539506/ Link: https://lore.kernel.org/r/1685036458-22683-9-git-send-email-quic_khsieh@quicinc.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
This commit is contained in:
parent
625cbb0770
commit
761c629d18
3 changed files with 36 additions and 8 deletions
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@ -1834,7 +1834,8 @@ dpu_encoder_dsc_initial_line_calc(struct drm_dsc_config *dsc,
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return DIV_ROUND_UP(total_pixels, dsc->slice_width);
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}
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static void dpu_encoder_dsc_pipe_cfg(struct dpu_hw_dsc *hw_dsc,
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static void dpu_encoder_dsc_pipe_cfg(struct dpu_hw_ctl *ctl,
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struct dpu_hw_dsc *hw_dsc,
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struct dpu_hw_pingpong *hw_pp,
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struct drm_dsc_config *dsc,
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u32 common_mode,
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@ -1854,6 +1855,9 @@ static void dpu_encoder_dsc_pipe_cfg(struct dpu_hw_dsc *hw_dsc,
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if (hw_pp->ops.enable_dsc)
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hw_pp->ops.enable_dsc(hw_pp);
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if (ctl->ops.update_pending_flush_dsc)
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ctl->ops.update_pending_flush_dsc(ctl, hw_dsc->idx);
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}
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static void dpu_encoder_prep_dsc(struct dpu_encoder_virt *dpu_enc,
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@ -1861,6 +1865,7 @@ static void dpu_encoder_prep_dsc(struct dpu_encoder_virt *dpu_enc,
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{
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/* coding only for 2LM, 2enc, 1 dsc config */
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struct dpu_encoder_phys *enc_master = dpu_enc->cur_master;
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struct dpu_hw_ctl *ctl = enc_master->hw_ctl;
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struct dpu_hw_dsc *hw_dsc[MAX_CHANNELS_PER_ENC];
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struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC];
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int this_frame_slices;
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@ -1898,7 +1903,8 @@ static void dpu_encoder_prep_dsc(struct dpu_encoder_virt *dpu_enc,
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initial_lines = dpu_encoder_dsc_initial_line_calc(dsc, enc_ip_w);
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for (i = 0; i < MAX_CHANNELS_PER_ENC; i++)
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dpu_encoder_dsc_pipe_cfg(hw_dsc[i], hw_pp[i], dsc, dsc_common_mode, initial_lines);
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dpu_encoder_dsc_pipe_cfg(ctl, hw_dsc[i], hw_pp[i],
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dsc, dsc_common_mode, initial_lines);
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}
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void dpu_encoder_prepare_for_kickoff(struct drm_encoder *drm_enc)
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@ -103,6 +103,7 @@ static inline void dpu_hw_ctl_clear_pending_flush(struct dpu_hw_ctl *ctx)
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ctx->pending_intf_flush_mask = 0;
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ctx->pending_wb_flush_mask = 0;
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ctx->pending_merge_3d_flush_mask = 0;
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ctx->pending_dsc_flush_mask = 0;
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memset(ctx->pending_dspp_flush_mask, 0,
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sizeof(ctx->pending_dspp_flush_mask));
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@ -142,6 +143,11 @@ static inline void dpu_hw_ctl_trigger_flush_v1(struct dpu_hw_ctl *ctx)
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CTL_DSPP_n_FLUSH(dspp - DSPP_0),
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ctx->pending_dspp_flush_mask[dspp - DSPP_0]);
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}
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if (ctx->pending_flush_mask & BIT(DSC_IDX))
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DPU_REG_WRITE(&ctx->hw, CTL_DSC_FLUSH,
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ctx->pending_dsc_flush_mask);
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DPU_REG_WRITE(&ctx->hw, CTL_FLUSH, ctx->pending_flush_mask);
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}
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@ -288,6 +294,13 @@ static void dpu_hw_ctl_update_pending_flush_merge_3d_v1(struct dpu_hw_ctl *ctx,
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ctx->pending_flush_mask |= BIT(MERGE_3D_IDX);
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}
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static void dpu_hw_ctl_update_pending_flush_dsc_v1(struct dpu_hw_ctl *ctx,
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enum dpu_dsc dsc_num)
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{
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ctx->pending_dsc_flush_mask |= BIT(dsc_num - DSC_0);
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ctx->pending_flush_mask |= BIT(DSC_IDX);
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}
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static void dpu_hw_ctl_update_pending_flush_dspp(struct dpu_hw_ctl *ctx,
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enum dpu_dspp dspp, u32 dspp_sub_blk)
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{
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@ -499,9 +512,6 @@ static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx,
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if ((test_bit(DPU_CTL_VM_CFG, &ctx->caps->features)))
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mode_sel = CTL_DEFAULT_GROUP_ID << 28;
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if (cfg->dsc)
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DPU_REG_WRITE(&ctx->hw, CTL_DSC_FLUSH, cfg->dsc);
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if (cfg->intf_mode_sel == DPU_CTL_MODE_SEL_CMD)
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mode_sel |= BIT(17);
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@ -521,10 +531,9 @@ static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx,
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if (cfg->merge_3d)
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DPU_REG_WRITE(c, CTL_MERGE_3D_ACTIVE,
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BIT(cfg->merge_3d - MERGE_3D_0));
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if (cfg->dsc) {
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DPU_REG_WRITE(&ctx->hw, CTL_FLUSH, BIT(DSC_IDX));
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if (cfg->dsc)
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DPU_REG_WRITE(c, CTL_DSC_ACTIVE, cfg->dsc);
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}
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}
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static void dpu_hw_ctl_intf_cfg(struct dpu_hw_ctl *ctx,
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@ -627,6 +636,8 @@ static void _setup_ctl_ops(struct dpu_hw_ctl_ops *ops,
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ops->update_pending_flush_merge_3d =
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dpu_hw_ctl_update_pending_flush_merge_3d_v1;
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ops->update_pending_flush_wb = dpu_hw_ctl_update_pending_flush_wb_v1;
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ops->update_pending_flush_dsc =
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dpu_hw_ctl_update_pending_flush_dsc_v1;
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} else {
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ops->trigger_flush = dpu_hw_ctl_trigger_flush;
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ops->setup_intf_cfg = dpu_hw_ctl_intf_cfg;
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@ -157,6 +157,15 @@ struct dpu_hw_ctl_ops {
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void (*update_pending_flush_dspp)(struct dpu_hw_ctl *ctx,
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enum dpu_dspp blk, u32 dspp_sub_blk);
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/**
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* OR in the given flushbits to the cached pending_(dsc_)flush_mask
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* No effect on hardware
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* @ctx: ctl path ctx pointer
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* @blk: interface block index
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*/
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void (*update_pending_flush_dsc)(struct dpu_hw_ctl *ctx,
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enum dpu_dsc blk);
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/**
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* Write the value of the pending_flush_mask to hardware
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* @ctx : ctl path ctx pointer
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@ -229,6 +238,7 @@ struct dpu_hw_ctl_ops {
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* @pending_flush_mask: storage for pending ctl_flush managed via ops
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* @pending_intf_flush_mask: pending INTF flush
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* @pending_wb_flush_mask: pending WB flush
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* @pending_dsc_flush_mask: pending DSC flush
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* @ops: operation list
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*/
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struct dpu_hw_ctl {
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@ -245,6 +255,7 @@ struct dpu_hw_ctl {
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u32 pending_wb_flush_mask;
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u32 pending_merge_3d_flush_mask;
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u32 pending_dspp_flush_mask[DSPP_MAX - DSPP_0];
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u32 pending_dsc_flush_mask;
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/* ops */
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struct dpu_hw_ctl_ops ops;
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