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RISC-V: Fix counter restart during overflow for RV32
commitacc1b919f4
upstream. Pass the upper half of the initial value of the counter correctly for RV32. Fixes:4905ec2fb7
("RISC-V: Add sscofpmf extension support") Signed-off-by: Atish Patra <atishp@rivosinc.com> Reviewed-by: Guo Ren <guoren@kernel.org> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20220711174632.4186047-2-atishp@rivosinc.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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@ -525,8 +525,13 @@ static inline void pmu_sbi_start_overflow_mask(struct riscv_pmu *pmu,
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hwc = &event->hw;
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max_period = riscv_pmu_ctr_get_width_mask(event);
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init_val = local64_read(&hwc->prev_count) & max_period;
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#if defined(CONFIG_32BIT)
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sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, idx, 1,
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flag, init_val, init_val >> 32, 0);
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#else
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sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, idx, 1,
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flag, init_val, 0, 0);
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#endif
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}
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ctr_ovf_mask = ctr_ovf_mask >> 1;
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idx++;
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