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drm/i915/dsb: Evade transcoder undelayed vblank when using DSB
We want to start the DSB execution from the transcoder's undelayed vblank, so in order to guarantee atomicity with the all the other mmio register writes we need to evade both vblanks. Note that currently we don't add any vblank delay, so this is effectively a nop. But in the future when we start to program double buffered registers from the DSB we'll need to delay the pipe's vblank to provide the register programming "window2" for the DSB. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230606191504.18099-15-ville.syrjala@linux.intel.com Reviewed-by: Uma Shankar <uma.shankar@intel.com>
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@ -516,8 +516,11 @@ static void intel_crtc_vblank_evade_scanlines(struct intel_atomic_state *state,
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* M/N and TRANS_VTOTAL are double buffered on the transcoder's
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* undelayed vblank, so with seamless M/N and LRR we must evade
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* both vblanks.
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*
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* DSB execution waits for the transcoder's undelayed vblank,
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* hence we must kick off the commit before that.
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*/
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if (new_crtc_state->update_m_n || new_crtc_state->update_lrr)
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if (new_crtc_state->dsb || new_crtc_state->update_m_n || new_crtc_state->update_lrr)
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*min -= adjusted_mode->crtc_vblank_start - adjusted_mode->crtc_vdisplay;
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}
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