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clk: ti: am43xx: add new clkctrl data for am43xx
The new clkctrl data layout for am43xx is split based on clockdomain boundaries. Previously the split was based on CM boundaries. This patch adds the new data as separate data entity, retaining the compatibility data also for now. The compatibility data can be removed once no longer needed. Signed-off-by: Tero Kristo <t-kristo@ti.com> Tested-by: Tony Lindgren <tony@atomide.com>
This commit is contained in:
Tero Kristo
parent
131ee08f3f
commit
76a1049b84
3 changed files with 268 additions and 5 deletions
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@ -23,11 +23,263 @@
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#include "clock.h"
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static const struct omap_clkctrl_reg_data am4_l3s_tsc_clkctrl_regs[] __initconst = {
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{ AM4_L3S_TSC_ADC_TSC_CLKCTRL, NULL, CLKF_SW_SUP, "adc_tsc_fck" },
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{ 0 },
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};
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static const char * const am4_synctimer_32kclk_parents[] __initconst = {
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"mux_synctimer32k_ck",
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NULL,
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};
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static const struct omap_clkctrl_bit_data am4_counter_32k_bit_data[] __initconst = {
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{ 8, TI_CLK_GATE, am4_synctimer_32kclk_parents, NULL },
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{ 0 },
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};
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static const struct omap_clkctrl_reg_data am4_l4_wkup_aon_clkctrl_regs[] __initconst = {
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{ AM4_L4_WKUP_AON_WKUP_M3_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "sys_clkin_ck" },
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{ AM4_L4_WKUP_AON_COUNTER_32K_CLKCTRL, am4_counter_32k_bit_data, CLKF_SW_SUP, "l4-wkup-aon-clkctrl:0008:8" },
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{ 0 },
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};
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static const char * const am4_gpio0_dbclk_parents[] __initconst = {
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"gpio0_dbclk_mux_ck",
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NULL,
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};
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static const struct omap_clkctrl_bit_data am4_gpio1_bit_data[] __initconst = {
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{ 8, TI_CLK_GATE, am4_gpio0_dbclk_parents, NULL },
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{ 0 },
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};
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static const struct omap_clkctrl_reg_data am4_l4_wkup_clkctrl_regs[] __initconst = {
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{ AM4_L4_WKUP_L4_WKUP_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin_ck" },
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{ AM4_L4_WKUP_TIMER1_CLKCTRL, NULL, CLKF_SW_SUP, "timer1_fck" },
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{ AM4_L4_WKUP_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "wdt1_fck" },
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{ AM4_L4_WKUP_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck" },
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{ AM4_L4_WKUP_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck" },
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{ AM4_L4_WKUP_SMARTREFLEX0_CLKCTRL, NULL, CLKF_SW_SUP, "smartreflex0_fck" },
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{ AM4_L4_WKUP_SMARTREFLEX1_CLKCTRL, NULL, CLKF_SW_SUP, "smartreflex1_fck" },
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{ AM4_L4_WKUP_CONTROL_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin_ck" },
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{ AM4_L4_WKUP_GPIO1_CLKCTRL, am4_gpio1_bit_data, CLKF_SW_SUP, "sys_clkin_ck" },
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{ 0 },
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};
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static const struct omap_clkctrl_reg_data am4_mpu_clkctrl_regs[] __initconst = {
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{ AM4_MPU_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_mpu_m2_ck" },
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{ 0 },
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};
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static const struct omap_clkctrl_reg_data am4_gfx_l3_clkctrl_regs[] __initconst = {
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{ AM4_GFX_L3_GFX_CLKCTRL, NULL, CLKF_SW_SUP, "gfx_fck_div_ck" },
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{ 0 },
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};
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static const struct omap_clkctrl_reg_data am4_l4_rtc_clkctrl_regs[] __initconst = {
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{ AM4_L4_RTC_RTC_CLKCTRL, NULL, CLKF_SW_SUP, "clk_32768_ck" },
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{ 0 },
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};
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static const struct omap_clkctrl_reg_data am4_l3_clkctrl_regs[] __initconst = {
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{ AM4_L3_L3_MAIN_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
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{ AM4_L3_AES_CLKCTRL, NULL, CLKF_SW_SUP, "aes0_fck" },
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{ AM4_L3_DES_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
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{ AM4_L3_L3_INSTR_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
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{ AM4_L3_OCMCRAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
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{ AM4_L3_SHAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
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{ AM4_L3_TPCC_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
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{ AM4_L3_TPTC0_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
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{ AM4_L3_TPTC1_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
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{ AM4_L3_TPTC2_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
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{ AM4_L3_L4_HS_CLKCTRL, NULL, CLKF_SW_SUP, "l4hs_gclk" },
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{ 0 },
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};
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static const char * const am4_usb_otg_ss0_refclk960m_parents[] __initconst = {
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"dpll_per_clkdcoldo",
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NULL,
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};
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static const struct omap_clkctrl_bit_data am4_usb_otg_ss0_bit_data[] __initconst = {
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{ 8, TI_CLK_GATE, am4_usb_otg_ss0_refclk960m_parents, NULL },
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{ 0 },
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};
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static const struct omap_clkctrl_bit_data am4_usb_otg_ss1_bit_data[] __initconst = {
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{ 8, TI_CLK_GATE, am4_usb_otg_ss0_refclk960m_parents, NULL },
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{ 0 },
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};
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static const struct omap_clkctrl_reg_data am4_l3s_clkctrl_regs[] __initconst = {
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{ AM4_L3S_VPFE0_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
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{ AM4_L3S_VPFE1_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
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{ AM4_L3S_GPMC_CLKCTRL, NULL, CLKF_SW_SUP, "l3s_gclk" },
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{ AM4_L3S_MCASP0_CLKCTRL, NULL, CLKF_SW_SUP, "mcasp0_fck" },
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{ AM4_L3S_MCASP1_CLKCTRL, NULL, CLKF_SW_SUP, "mcasp1_fck" },
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{ AM4_L3S_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" },
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{ AM4_L3S_QSPI_CLKCTRL, NULL, CLKF_SW_SUP, "l3s_gclk" },
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{ AM4_L3S_USB_OTG_SS0_CLKCTRL, am4_usb_otg_ss0_bit_data, CLKF_SW_SUP, "l3s_gclk" },
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{ AM4_L3S_USB_OTG_SS1_CLKCTRL, am4_usb_otg_ss1_bit_data, CLKF_SW_SUP, "l3s_gclk" },
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{ 0 },
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};
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static const struct omap_clkctrl_reg_data am4_pruss_ocp_clkctrl_regs[] __initconst = {
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{ AM4_PRUSS_OCP_PRUSS_CLKCTRL, NULL, CLKF_SW_SUP, "pruss_ocp_gclk" },
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{ 0 },
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};
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static const char * const am4_gpio1_dbclk_parents[] __initconst = {
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"clkdiv32k_ick",
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NULL,
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};
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static const struct omap_clkctrl_bit_data am4_gpio2_bit_data[] __initconst = {
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{ 8, TI_CLK_GATE, am4_gpio1_dbclk_parents, NULL },
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{ 0 },
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};
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static const struct omap_clkctrl_bit_data am4_gpio3_bit_data[] __initconst = {
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{ 8, TI_CLK_GATE, am4_gpio1_dbclk_parents, NULL },
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{ 0 },
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};
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static const struct omap_clkctrl_bit_data am4_gpio4_bit_data[] __initconst = {
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{ 8, TI_CLK_GATE, am4_gpio1_dbclk_parents, NULL },
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{ 0 },
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};
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static const struct omap_clkctrl_bit_data am4_gpio5_bit_data[] __initconst = {
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{ 8, TI_CLK_GATE, am4_gpio1_dbclk_parents, NULL },
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{ 0 },
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};
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static const struct omap_clkctrl_bit_data am4_gpio6_bit_data[] __initconst = {
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{ 8, TI_CLK_GATE, am4_gpio1_dbclk_parents, NULL },
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{ 0 },
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};
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static const struct omap_clkctrl_reg_data am4_l4ls_clkctrl_regs[] __initconst = {
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{ AM4_L4LS_L4_LS_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
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{ AM4_L4LS_D_CAN0_CLKCTRL, NULL, CLKF_SW_SUP, "dcan0_fck" },
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{ AM4_L4LS_D_CAN1_CLKCTRL, NULL, CLKF_SW_SUP, "dcan1_fck" },
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{ AM4_L4LS_EPWMSS0_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
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{ AM4_L4LS_EPWMSS1_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
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{ AM4_L4LS_EPWMSS2_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
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{ AM4_L4LS_EPWMSS3_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
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{ AM4_L4LS_EPWMSS4_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
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{ AM4_L4LS_EPWMSS5_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
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{ AM4_L4LS_ELM_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
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{ AM4_L4LS_GPIO2_CLKCTRL, am4_gpio2_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
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{ AM4_L4LS_GPIO3_CLKCTRL, am4_gpio3_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
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{ AM4_L4LS_GPIO4_CLKCTRL, am4_gpio4_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
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{ AM4_L4LS_GPIO5_CLKCTRL, am4_gpio5_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
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{ AM4_L4LS_GPIO6_CLKCTRL, am4_gpio6_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
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{ AM4_L4LS_HDQ1W_CLKCTRL, NULL, CLKF_SW_SUP, "func_12m_clk" },
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{ AM4_L4LS_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
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{ AM4_L4LS_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
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{ AM4_L4LS_MAILBOX_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
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{ AM4_L4LS_MMC1_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" },
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{ AM4_L4LS_MMC2_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" },
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{ AM4_L4LS_RNG_CLKCTRL, NULL, CLKF_SW_SUP, "rng_fck" },
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{ AM4_L4LS_SPI0_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
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{ AM4_L4LS_SPI1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
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{ AM4_L4LS_SPI2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
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{ AM4_L4LS_SPI3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
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{ AM4_L4LS_SPI4_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
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{ AM4_L4LS_SPINLOCK_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
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{ AM4_L4LS_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "timer2_fck" },
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{ AM4_L4LS_TIMER3_CLKCTRL, NULL, CLKF_SW_SUP, "timer3_fck" },
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{ AM4_L4LS_TIMER4_CLKCTRL, NULL, CLKF_SW_SUP, "timer4_fck" },
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{ AM4_L4LS_TIMER5_CLKCTRL, NULL, CLKF_SW_SUP, "timer5_fck" },
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{ AM4_L4LS_TIMER6_CLKCTRL, NULL, CLKF_SW_SUP, "timer6_fck" },
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{ AM4_L4LS_TIMER7_CLKCTRL, NULL, CLKF_SW_SUP, "timer7_fck" },
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{ AM4_L4LS_TIMER8_CLKCTRL, NULL, CLKF_SW_SUP, "timer8_fck" },
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{ AM4_L4LS_TIMER9_CLKCTRL, NULL, CLKF_SW_SUP, "timer9_fck" },
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{ AM4_L4LS_TIMER10_CLKCTRL, NULL, CLKF_SW_SUP, "timer10_fck" },
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{ AM4_L4LS_TIMER11_CLKCTRL, NULL, CLKF_SW_SUP, "timer11_fck" },
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{ AM4_L4LS_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
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{ AM4_L4LS_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
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{ AM4_L4LS_UART4_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
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{ AM4_L4LS_UART5_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
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{ AM4_L4LS_UART6_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
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{ AM4_L4LS_OCP2SCP0_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
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{ AM4_L4LS_OCP2SCP1_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
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{ 0 },
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};
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static const struct omap_clkctrl_reg_data am4_emif_clkctrl_regs[] __initconst = {
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{ AM4_EMIF_EMIF_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_ddr_m2_ck" },
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{ 0 },
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};
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static const struct omap_clkctrl_reg_data am4_dss_clkctrl_regs[] __initconst = {
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{ AM4_DSS_DSS_CORE_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_SET_RATE_PARENT, "disp_clk" },
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{ 0 },
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};
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static const struct omap_clkctrl_reg_data am4_cpsw_125mhz_clkctrl_regs[] __initconst = {
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{ AM4_CPSW_125MHZ_CPGMAC0_CLKCTRL, NULL, CLKF_SW_SUP, "cpsw_125mhz_gclk" },
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{ 0 },
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};
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const struct omap_clkctrl_data am4_clkctrl_data[] __initconst = {
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{ 0x44df2920, am4_l3s_tsc_clkctrl_regs },
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{ 0x44df2a28, am4_l4_wkup_aon_clkctrl_regs },
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{ 0x44df2a20, am4_l4_wkup_clkctrl_regs },
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{ 0x44df8320, am4_mpu_clkctrl_regs },
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{ 0x44df8420, am4_gfx_l3_clkctrl_regs },
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{ 0x44df8520, am4_l4_rtc_clkctrl_regs },
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{ 0x44df8820, am4_l3_clkctrl_regs },
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{ 0x44df8868, am4_l3s_clkctrl_regs },
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{ 0x44df8b20, am4_pruss_ocp_clkctrl_regs },
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{ 0x44df8c20, am4_l4ls_clkctrl_regs },
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{ 0x44df8f20, am4_emif_clkctrl_regs },
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{ 0x44df9220, am4_dss_clkctrl_regs },
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{ 0x44df9320, am4_cpsw_125mhz_clkctrl_regs },
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{ 0 },
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};
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const struct omap_clkctrl_data am438x_clkctrl_data[] __initconst = {
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{ 0x44df2920, am4_l3s_tsc_clkctrl_regs },
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{ 0x44df2a28, am4_l4_wkup_aon_clkctrl_regs },
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{ 0x44df2a20, am4_l4_wkup_clkctrl_regs },
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{ 0x44df8320, am4_mpu_clkctrl_regs },
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{ 0x44df8420, am4_gfx_l3_clkctrl_regs },
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{ 0x44df8820, am4_l3_clkctrl_regs },
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{ 0x44df8868, am4_l3s_clkctrl_regs },
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{ 0x44df8b20, am4_pruss_ocp_clkctrl_regs },
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{ 0x44df8c20, am4_l4ls_clkctrl_regs },
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{ 0x44df8f20, am4_emif_clkctrl_regs },
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{ 0x44df9220, am4_dss_clkctrl_regs },
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{ 0x44df9320, am4_cpsw_125mhz_clkctrl_regs },
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{ 0 },
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};
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static struct ti_dt_clk am43xx_clks[] = {
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DT_CLK(NULL, "timer_32k_ck", "clkdiv32k_ick"),
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DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"),
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DT_CLK(NULL, "gpio0_dbclk", "l4-wkup-clkctrl:0148:8"),
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DT_CLK(NULL, "gpio1_dbclk", "l4ls-clkctrl:0058:8"),
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DT_CLK(NULL, "gpio2_dbclk", "l4ls-clkctrl:0060:8"),
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DT_CLK(NULL, "gpio3_dbclk", "l4ls-clkctrl:0068:8"),
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DT_CLK(NULL, "gpio4_dbclk", "l4ls-clkctrl:0070:8"),
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DT_CLK(NULL, "gpio5_dbclk", "l4ls-clkctrl:0078:8"),
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DT_CLK(NULL, "synctimer_32kclk", "l4-wkup-aon-clkctrl:0008:8"),
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DT_CLK(NULL, "usb_otg_ss0_refclk960m", "l3s-clkctrl:01f8:8"),
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DT_CLK(NULL, "usb_otg_ss1_refclk960m", "l3s-clkctrl:0200:8"),
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{ .node_name = NULL },
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};
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int __init am43xx_dt_clk_init(void)
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{
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struct clk *clk1, *clk2;
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ti_dt_clocks_register(am43xx_compat_clks);
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if (ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT)
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ti_dt_clocks_register(am43xx_compat_clks);
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else
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ti_dt_clocks_register(am43xx_clks);
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omap2_clk_disable_autoidle_all();
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@ -475,10 +475,19 @@ static void __init _ti_omap4_clkctrl_setup(struct device_node *node)
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}
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#endif
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#ifdef CONFIG_SOC_AM43XX
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if (of_machine_is_compatible("ti,am4372"))
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data = am4_clkctrl_compat_data;
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if (of_machine_is_compatible("ti,am438x"))
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data = am438x_clkctrl_compat_data;
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if (of_machine_is_compatible("ti,am4372")) {
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if (ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT)
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data = am4_clkctrl_compat_data;
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else
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data = am4_clkctrl_data;
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}
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if (of_machine_is_compatible("ti,am438x")) {
|
||||
if (ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT)
|
||||
data = am438x_clkctrl_compat_data;
|
||||
else
|
||||
data = am438x_clkctrl_data;
|
||||
}
|
||||
#endif
|
||||
#ifdef CONFIG_SOC_TI81XX
|
||||
if (of_machine_is_compatible("ti,dm814"))
|
||||
|
|
|
|||
|
|
@ -187,8 +187,10 @@ extern const struct omap_clkctrl_data dra7_clkctrl_data[];
|
|||
extern const struct omap_clkctrl_data am3_clkctrl_data[];
|
||||
extern const struct omap_clkctrl_data am3_clkctrl_compat_data[];
|
||||
extern struct ti_dt_clk am33xx_compat_clks[];
|
||||
extern const struct omap_clkctrl_data am4_clkctrl_data[];
|
||||
extern const struct omap_clkctrl_data am4_clkctrl_compat_data[];
|
||||
extern struct ti_dt_clk am43xx_compat_clks[];
|
||||
extern const struct omap_clkctrl_data am438x_clkctrl_data[];
|
||||
extern const struct omap_clkctrl_data am438x_clkctrl_compat_data[];
|
||||
extern const struct omap_clkctrl_data dm814_clkctrl_data[];
|
||||
extern const struct omap_clkctrl_data dm816_clkctrl_data[];
|
||||
|
|
|
|||
Loading…
Reference in a new issue