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spi/spi-fsl-spi: Add support for gpio chipselects for GRLIB type cores
This relies upon of_spi_register_master to find out which gpios to use. Acked-by: Anton Vorontsov <anton@enomsg.org> Signed-off-by: Andreas Larsson <andreas@gaisler.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
This commit is contained in:
parent
447b0c7b93
commit
76a7498f69
2 changed files with 46 additions and 5 deletions
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@ -71,6 +71,7 @@ struct mpc8xxx_spi {
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#ifdef CONFIG_SPI_FSL_SPI
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#ifdef CONFIG_SPI_FSL_SPI
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int type;
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int type;
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int native_chipselects;
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u8 max_bits_per_word;
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u8 max_bits_per_word;
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void (*set_shifts)(u32 *rx_shift, u32 *tx_shift,
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void (*set_shifts)(u32 *rx_shift, u32 *tx_shift,
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@ -456,12 +456,46 @@ static int fsl_spi_setup(struct spi_device *spi)
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return retval;
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return retval;
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}
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}
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if (mpc8xxx_spi->type == TYPE_GRLIB) {
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if (gpio_is_valid(spi->cs_gpio)) {
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int desel;
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retval = gpio_request(spi->cs_gpio,
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dev_name(&spi->dev));
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if (retval)
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return retval;
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desel = !(spi->mode & SPI_CS_HIGH);
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retval = gpio_direction_output(spi->cs_gpio, desel);
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if (retval) {
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gpio_free(spi->cs_gpio);
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return retval;
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}
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} else if (spi->cs_gpio != -ENOENT) {
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if (spi->cs_gpio < 0)
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return spi->cs_gpio;
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return -EINVAL;
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}
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/* When spi->cs_gpio == -ENOENT, a hole in the phandle list
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* indicates to use native chipselect if present, or allow for
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* an always selected chip
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*/
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}
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/* Initialize chipselect - might be active for SPI_CS_HIGH mode */
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/* Initialize chipselect - might be active for SPI_CS_HIGH mode */
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fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE);
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fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE);
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return 0;
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return 0;
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}
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}
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static void fsl_spi_cleanup(struct spi_device *spi)
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{
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struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
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if (mpc8xxx_spi->type == TYPE_GRLIB && gpio_is_valid(spi->cs_gpio))
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gpio_free(spi->cs_gpio);
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}
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static void fsl_spi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events)
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static void fsl_spi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events)
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{
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{
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struct fsl_spi_reg *reg_base = mspi->reg_base;
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struct fsl_spi_reg *reg_base = mspi->reg_base;
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@ -529,9 +563,13 @@ static void fsl_spi_grlib_cs_control(struct spi_device *spi, bool on)
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u32 slvsel;
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u32 slvsel;
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u16 cs = spi->chip_select;
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u16 cs = spi->chip_select;
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if (gpio_is_valid(spi->cs_gpio)) {
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gpio_set_value(spi->cs_gpio, on);
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} else if (cs < mpc8xxx_spi->native_chipselects) {
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slvsel = mpc8xxx_spi_read_reg(®_base->slvsel);
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slvsel = mpc8xxx_spi_read_reg(®_base->slvsel);
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slvsel = on ? (slvsel | (1 << cs)) : (slvsel & ~(1 << cs));
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slvsel = on ? (slvsel | (1 << cs)) : (slvsel & ~(1 << cs));
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mpc8xxx_spi_write_reg(®_base->slvsel, slvsel);
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mpc8xxx_spi_write_reg(®_base->slvsel, slvsel);
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}
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}
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}
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static void fsl_spi_grlib_probe(struct device *dev)
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static void fsl_spi_grlib_probe(struct device *dev)
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@ -550,11 +588,12 @@ static void fsl_spi_grlib_probe(struct device *dev)
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if (mbits)
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if (mbits)
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mpc8xxx_spi->max_bits_per_word = mbits + 1;
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mpc8xxx_spi->max_bits_per_word = mbits + 1;
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master->num_chipselect = 1; /* Allow for an always selected chip */
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mpc8xxx_spi->native_chipselects = 0;
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if (SPCAP_SSEN(capabilities)) {
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if (SPCAP_SSEN(capabilities)) {
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master->num_chipselect = SPCAP_SSSZ(capabilities);
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mpc8xxx_spi->native_chipselects = SPCAP_SSSZ(capabilities);
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mpc8xxx_spi_write_reg(®_base->slvsel, 0xffffffff);
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mpc8xxx_spi_write_reg(®_base->slvsel, 0xffffffff);
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}
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}
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master->num_chipselect = mpc8xxx_spi->native_chipselects;
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pdata->cs_control = fsl_spi_grlib_cs_control;
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pdata->cs_control = fsl_spi_grlib_cs_control;
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}
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}
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@ -581,6 +620,7 @@ static struct spi_master * fsl_spi_probe(struct device *dev,
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goto err_probe;
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goto err_probe;
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master->setup = fsl_spi_setup;
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master->setup = fsl_spi_setup;
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master->cleanup = fsl_spi_cleanup;
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mpc8xxx_spi = spi_master_get_devdata(master);
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mpc8xxx_spi = spi_master_get_devdata(master);
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mpc8xxx_spi->spi_do_one_msg = fsl_spi_do_one_msg;
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mpc8xxx_spi->spi_do_one_msg = fsl_spi_do_one_msg;
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