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riscv: Setup exception vector for nommu platform

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Exception vector is missing on nommu platform and that is an issue.
This patch is tested in Sipeed Maix Bit Dev Board.

Fixes: 79b1feba54 ("RISC-V: Setup exception vector early")
Suggested-by: Anup Patel <anup@brainfault.org>
Suggested-by: Atish Patra <atishp@atishpatra.org>
Signed-off-by: Qiu Wenbo <qiuwenbo@phytium.com.cn>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
This commit is contained in:
Qiu Wenbo 2020-08-13 11:38:04 +08:00 committed by Palmer Dabbelt
parent dbf8381731
commit 76d4467a97
No known key found for this signature in database
GPG key ID: 2E1319F35FBB1889
1 changed files with 17 additions and 8 deletions
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25
arch/riscv/kernel/head.S
View file

@ -77,16 +77,10 @@ relocate:
csrw CSR_SATP, a0
.align 2
1:
/* Set trap vector to exception handler */
la a0, handle_exception
/* Set trap vector to spin forever to help debug */
la a0, .Lsecondary_park
csrw CSR_TVEC, a0
/*
* Set sup0 scratch register to 0, indicating to exception vector that
* we are presently executing in kernel.
*/
csrw CSR_SCRATCH, zero
/* Reload the global pointer */
.option push
.option norelax
@ -144,9 +138,23 @@ secondary_start_common:
la a0, swapper_pg_dir
call relocate
#endif
call setup_trap_vector
tail smp_callin
#endif /* CONFIG_SMP */
.align 2
setup_trap_vector:
/* Set trap vector to exception handler */
la a0, handle_exception
csrw CSR_TVEC, a0
/*
* Set sup0 scratch register to 0, indicating to exception vector that
* we are presently executing in kernel.
*/
csrw CSR_SCRATCH, zero
ret
.Lsecondary_park:
/* We lack SMP support or have too many harts, so park this hart */
wfi
@ -240,6 +248,7 @@ clear_bss_done:
call relocate
#endif /* CONFIG_MMU */
call setup_trap_vector
/* Restore C environment */
la tp, init_task
sw zero, TASK_TI_CPU(tp)