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dt-bindings: clock: exynos850: Add CMU_CPUCLK0 and CMU_CPUCL1
Document CPU clock management unit compatibles and add corresponding clock indices. Exynos850 has two CPU clusters (CL0 and CL1), each containing 4 Cortex-A55 cores. CPU PLLs are generating main CPU clocks for each cluster, and there are alternate ("switch") clocks that can be used temporarily while re-configuring the PLL for the new rate. ACLK, ATCLK, PCLKDBG and PERIPHCLK clocks are driving corresponding buses. CLK_CLUSTERx_SCLK are actual leaf CPU clocks and should be used to change CPU rates. Also some CoreSight clocks can be derived from DBG_USER (debug clock). Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Link: https://lore.kernel.org/r/20240224202053.25313-2-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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2 changed files with 96 additions and 0 deletions
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@ -36,6 +36,8 @@ properties:
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- samsung,exynos850-cmu-aud
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- samsung,exynos850-cmu-cmgp
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- samsung,exynos850-cmu-core
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- samsung,exynos850-cmu-cpucl0
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- samsung,exynos850-cmu-cpucl1
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- samsung,exynos850-cmu-dpu
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- samsung,exynos850-cmu-g3d
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- samsung,exynos850-cmu-hsi
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@ -152,6 +154,46 @@ allOf:
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- const: dout_core_mmc_embd
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- const: dout_core_sss
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- if:
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properties:
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compatible:
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contains:
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const: samsung,exynos850-cmu-cpucl0
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then:
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properties:
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clocks:
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items:
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- description: External reference clock (26 MHz)
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- description: CPUCL0 switch clock (from CMU_TOP)
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- description: CPUCL0 debug clock (from CMU_TOP)
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clock-names:
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items:
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- const: oscclk
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- const: dout_cpucl0_switch
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- const: dout_cpucl0_dbg
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- if:
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properties:
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compatible:
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contains:
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const: samsung,exynos850-cmu-cpucl1
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then:
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properties:
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clocks:
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items:
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- description: External reference clock (26 MHz)
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- description: CPUCL1 switch clock (from CMU_TOP)
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- description: CPUCL1 debug clock (from CMU_TOP)
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clock-names:
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items:
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- const: oscclk
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- const: dout_cpucl1_switch
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- const: dout_cpucl1_dbg
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- if:
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properties:
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compatible:
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@ -88,6 +88,18 @@
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#define CLK_MOUT_G3D_SWITCH 76
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#define CLK_GOUT_G3D_SWITCH 77
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#define CLK_DOUT_G3D_SWITCH 78
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#define CLK_MOUT_CPUCL0_DBG 79
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#define CLK_MOUT_CPUCL0_SWITCH 80
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#define CLK_GOUT_CPUCL0_DBG 81
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#define CLK_GOUT_CPUCL0_SWITCH 82
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#define CLK_DOUT_CPUCL0_DBG 83
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#define CLK_DOUT_CPUCL0_SWITCH 84
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#define CLK_MOUT_CPUCL1_DBG 85
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#define CLK_MOUT_CPUCL1_SWITCH 86
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#define CLK_GOUT_CPUCL1_DBG 87
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#define CLK_GOUT_CPUCL1_SWITCH 88
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#define CLK_DOUT_CPUCL1_DBG 89
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#define CLK_DOUT_CPUCL1_SWITCH 90
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/* CMU_APM */
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#define CLK_RCO_I3C_PMIC 1
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@ -195,6 +207,48 @@
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#define CLK_GOUT_CMGP_USI1_PCLK 14
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#define CLK_GOUT_SYSREG_CMGP_PCLK 15
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/* CMU_CPUCL0 */
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#define CLK_FOUT_CPUCL0_PLL 1
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#define CLK_MOUT_PLL_CPUCL0 2
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#define CLK_MOUT_CPUCL0_SWITCH_USER 3
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#define CLK_MOUT_CPUCL0_DBG_USER 4
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#define CLK_MOUT_CPUCL0_PLL 5
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#define CLK_DOUT_CPUCL0_CPU 6
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#define CLK_DOUT_CPUCL0_CMUREF 7
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#define CLK_DOUT_CPUCL0_PCLK 8
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#define CLK_DOUT_CLUSTER0_ACLK 9
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#define CLK_DOUT_CLUSTER0_ATCLK 10
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#define CLK_DOUT_CLUSTER0_PCLKDBG 11
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#define CLK_DOUT_CLUSTER0_PERIPHCLK 12
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#define CLK_GOUT_CLUSTER0_ATCLK 13
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#define CLK_GOUT_CLUSTER0_PCLK 14
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#define CLK_GOUT_CLUSTER0_PERIPHCLK 15
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#define CLK_GOUT_CLUSTER0_SCLK 16
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#define CLK_GOUT_CPUCL0_CMU_CPUCL0_PCLK 17
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#define CLK_GOUT_CLUSTER0_CPU 18
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#define CLK_CLUSTER0_SCLK 19
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/* CMU_CPUCL1 */
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#define CLK_FOUT_CPUCL1_PLL 1
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#define CLK_MOUT_PLL_CPUCL1 2
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#define CLK_MOUT_CPUCL1_SWITCH_USER 3
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#define CLK_MOUT_CPUCL1_DBG_USER 4
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#define CLK_MOUT_CPUCL1_PLL 5
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#define CLK_DOUT_CPUCL1_CPU 6
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#define CLK_DOUT_CPUCL1_CMUREF 7
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#define CLK_DOUT_CPUCL1_PCLK 8
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#define CLK_DOUT_CLUSTER1_ACLK 9
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#define CLK_DOUT_CLUSTER1_ATCLK 10
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#define CLK_DOUT_CLUSTER1_PCLKDBG 11
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#define CLK_DOUT_CLUSTER1_PERIPHCLK 12
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#define CLK_GOUT_CLUSTER1_ATCLK 13
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#define CLK_GOUT_CLUSTER1_PCLK 14
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#define CLK_GOUT_CLUSTER1_PERIPHCLK 15
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#define CLK_GOUT_CLUSTER1_SCLK 16
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#define CLK_GOUT_CPUCL1_CMU_CPUCL1_PCLK 17
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#define CLK_GOUT_CLUSTER1_CPU 18
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#define CLK_CLUSTER1_SCLK 19
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/* CMU_G3D */
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#define CLK_FOUT_G3D_PLL 1
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#define CLK_MOUT_G3D_PLL 2
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