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drm/amdgpu/cik: move uvd tiling config setup into uvd code
Split uvd and gfx programming. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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parent
2b3a765d83
commit
76ed6cb017
2 changed files with 11 additions and 11 deletions
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@ -31,8 +31,6 @@
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#include "amdgpu_ucode.h"
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#include "clearstate_ci.h"
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#include "uvd/uvd_4_2_d.h"
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#include "dce/dce_8_0_d.h"
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#include "dce/dce_8_0_sh_mask.h"
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@ -1721,9 +1719,6 @@ static void gfx_v7_0_gpu_init(struct amdgpu_device *adev)
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WREG32(mmGB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
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WREG32(mmHDP_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
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WREG32(mmDMIF_ADDR_CALC, adev->gfx.config.gb_addr_config);
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WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
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WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
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WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
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gfx_v7_0_tiling_mode_table_init(adev);
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@ -4600,12 +4595,6 @@ static void gfx_v7_0_print_status(void *handle)
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RREG32(mmHDP_ADDR_CONFIG));
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dev_info(adev->dev, " DMIF_ADDR_CALC=0x%08X\n",
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RREG32(mmDMIF_ADDR_CALC));
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dev_info(adev->dev, " UVD_UDEC_ADDR_CONFIG=0x%08X\n",
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RREG32(mmUVD_UDEC_ADDR_CONFIG));
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dev_info(adev->dev, " UVD_UDEC_DB_ADDR_CONFIG=0x%08X\n",
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RREG32(mmUVD_UDEC_DB_ADDR_CONFIG));
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dev_info(adev->dev, " UVD_UDEC_DBW_ADDR_CONFIG=0x%08X\n",
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RREG32(mmUVD_UDEC_DBW_ADDR_CONFIG));
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dev_info(adev->dev, " CP_MEQ_THRESHOLDS=0x%08X\n",
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RREG32(mmCP_MEQ_THRESHOLDS));
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@ -576,6 +576,10 @@ static void uvd_v4_2_mc_resume(struct amdgpu_device *adev)
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addr = (adev->uvd.gpu_addr >> 32) & 0xFF;
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WREG32(mmUVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1 << 31));
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WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
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WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
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WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
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uvd_v4_2_init_cg(adev);
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}
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@ -777,6 +781,13 @@ static void uvd_v4_2_print_status(void *handle)
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RREG32(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL));
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dev_info(adev->dev, " UVD_CONTEXT_ID=0x%08X\n",
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RREG32(mmUVD_CONTEXT_ID));
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dev_info(adev->dev, " UVD_UDEC_ADDR_CONFIG=0x%08X\n",
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RREG32(mmUVD_UDEC_ADDR_CONFIG));
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dev_info(adev->dev, " UVD_UDEC_DB_ADDR_CONFIG=0x%08X\n",
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RREG32(mmUVD_UDEC_DB_ADDR_CONFIG));
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dev_info(adev->dev, " UVD_UDEC_DBW_ADDR_CONFIG=0x%08X\n",
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RREG32(mmUVD_UDEC_DBW_ADDR_CONFIG));
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}
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static int uvd_v4_2_set_interrupt_state(struct amdgpu_device *adev,
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