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clk: qcom: gcc-sdx65: switch to parent_hws

Browse source 
Change several entries of parent_data to use parent_hws instead, which
results in slightly more ovbious code.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230103145515.1164020-11-dmitry.baryshkov@linaro.org
This commit is contained in:
Dmitry Baryshkov 2023-01-03 16:55:04 +02:00 committed by Bjorn Andersson
parent a28c07fc91
commit 76ffb19210
1 changed files with 54 additions and 55 deletions
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109
drivers/clk/qcom/gcc-sdx65.c
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@ -634,8 +634,8 @@ static struct clk_regmap_div gcc_cpuss_ahb_postdiv_clk_src = {
.width = 4,
.clkr.hw.init = &(struct clk_init_data) {
.name = "gcc_cpuss_ahb_postdiv_clk_src",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_cpuss_ahb_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&gcc_cpuss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@ -649,8 +649,8 @@ static struct clk_regmap_div gcc_usb30_mock_utmi_postdiv_clk_src = {
.width = 4,
.clkr.hw.init = &(struct clk_init_data) {
.name = "gcc_usb30_mock_utmi_postdiv_clk_src",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_usb30_mock_utmi_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb30_mock_utmi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@ -692,8 +692,8 @@ static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup1_i2c_apps_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_blsp1_qup1_i2c_apps_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&gcc_blsp1_qup1_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@ -710,8 +710,8 @@ static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup1_spi_apps_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_blsp1_qup1_spi_apps_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&gcc_blsp1_qup1_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@ -728,8 +728,8 @@ static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup2_i2c_apps_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_blsp1_qup2_i2c_apps_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&gcc_blsp1_qup2_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@ -746,8 +746,8 @@ static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup2_spi_apps_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_blsp1_qup2_spi_apps_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&gcc_blsp1_qup2_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@ -764,8 +764,8 @@ static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup3_i2c_apps_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_blsp1_qup3_i2c_apps_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&gcc_blsp1_qup3_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@ -782,8 +782,8 @@ static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup3_spi_apps_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_blsp1_qup3_spi_apps_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&gcc_blsp1_qup3_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@ -800,8 +800,8 @@ static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup4_i2c_apps_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_blsp1_qup4_i2c_apps_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&gcc_blsp1_qup4_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@ -818,8 +818,8 @@ static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup4_spi_apps_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_blsp1_qup4_spi_apps_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&gcc_blsp1_qup4_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@ -849,8 +849,8 @@ static struct clk_branch gcc_blsp1_uart1_apps_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart1_apps_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_blsp1_uart1_apps_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&gcc_blsp1_uart1_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@ -867,8 +867,8 @@ static struct clk_branch gcc_blsp1_uart2_apps_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart2_apps_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_blsp1_uart2_apps_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&gcc_blsp1_uart2_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@ -885,8 +885,8 @@ static struct clk_branch gcc_blsp1_uart3_apps_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart3_apps_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_blsp1_uart3_apps_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&gcc_blsp1_uart3_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@ -903,8 +903,8 @@ static struct clk_branch gcc_blsp1_uart4_apps_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart4_apps_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_blsp1_uart4_apps_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&gcc_blsp1_uart4_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@ -936,8 +936,8 @@ static struct clk_branch gcc_gp1_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp1_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_gp1_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&gcc_gp1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@ -954,8 +954,8 @@ static struct clk_branch gcc_gp2_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp2_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_gp2_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&gcc_gp2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@ -972,8 +972,8 @@ static struct clk_branch gcc_gp3_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp3_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_gp3_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&gcc_gp3_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@ -1017,8 +1017,8 @@ static struct clk_branch gcc_pcie_aux_clk = {
.enable_mask = BIT(3),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_aux_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_pcie_aux_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcie_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@ -1073,8 +1073,8 @@ static struct clk_branch gcc_pcie_pipe_clk = {
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_pipe_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_pcie_pipe_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcie_pipe_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@ -1093,8 +1093,8 @@ static struct clk_branch gcc_pcie_rchng_phy_clk = {
.enable_mask = BIT(7),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_rchng_phy_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_pcie_rchng_phy_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcie_rchng_phy_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@ -1113,8 +1113,8 @@ static struct clk_branch gcc_pcie_sleep_clk = {
.enable_mask = BIT(6),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_sleep_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_pcie_aux_phy_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcie_aux_phy_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@ -1161,8 +1161,8 @@ static struct clk_branch gcc_pdm2_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pdm2_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_pdm2_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&gcc_pdm2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@ -1233,8 +1233,8 @@ static struct clk_branch gcc_sdcc1_apps_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_apps_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_sdcc1_apps_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&gcc_sdcc1_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@ -1251,8 +1251,8 @@ static struct clk_branch gcc_usb30_master_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_master_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_usb30_master_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb30_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@ -1269,9 +1269,8 @@ static struct clk_branch gcc_usb30_mock_utmi_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_mock_utmi_clk",
.parent_data = &(const struct clk_parent_data){
.hw =
&gcc_usb30_mock_utmi_postdiv_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb30_mock_utmi_postdiv_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@ -1327,8 +1326,8 @@ static struct clk_branch gcc_usb3_phy_aux_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_phy_aux_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_usb3_phy_aux_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb3_phy_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@ -1369,8 +1368,8 @@ static struct clk_branch gcc_usb3_phy_pipe_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_phy_pipe_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_usb3_phy_pipe_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb3_phy_pipe_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,