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staging: sm750fb: setDisplayControl: rename local vairables
Remove HungarianCamelCase notation. Signed-off-by: Mike Rapoport <mike.rapoport@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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c436e6ba7e
commit
7755265a99
1 changed files with 25 additions and 25 deletions
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@ -9,25 +9,25 @@
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static void setDisplayControl(int ctrl, int disp_state)
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{
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/* state != 0 means turn on both timing & plane en_bit */
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unsigned long ulDisplayCtrlReg, ulReservedBits;
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unsigned long reg, reserved;
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int cnt;
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cnt = 0;
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/* Set the primary display control */
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if (!ctrl) {
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ulDisplayCtrlReg = PEEK32(PANEL_DISPLAY_CTRL);
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reg = PEEK32(PANEL_DISPLAY_CTRL);
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/* Turn on/off the Panel display control */
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if (disp_state) {
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/* Timing should be enabled first before enabling the plane
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* because changing at the same time does not guarantee that
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* the plane will also enabled or disabled.
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*/
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ulDisplayCtrlReg = FIELD_SET(ulDisplayCtrlReg,
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reg = FIELD_SET(reg,
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PANEL_DISPLAY_CTRL, TIMING, ENABLE);
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POKE32(PANEL_DISPLAY_CTRL, ulDisplayCtrlReg);
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POKE32(PANEL_DISPLAY_CTRL, reg);
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ulDisplayCtrlReg = FIELD_SET(ulDisplayCtrlReg,
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reg = FIELD_SET(reg,
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PANEL_DISPLAY_CTRL, PLANE, ENABLE);
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/* Added some masks to mask out the reserved bits.
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@ -35,7 +35,7 @@ static void setDisplayControl(int ctrl, int disp_state)
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* writing to the PRIMARY_DISPLAY_CTRL, therefore, the register
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* reserved bits are needed to be masked out.
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*/
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ulReservedBits = FIELD_SET(0, PANEL_DISPLAY_CTRL, RESERVED_1_MASK, ENABLE) |
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reserved = FIELD_SET(0, PANEL_DISPLAY_CTRL, RESERVED_1_MASK, ENABLE) |
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FIELD_SET(0, PANEL_DISPLAY_CTRL, RESERVED_2_MASK, ENABLE) |
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FIELD_SET(0, PANEL_DISPLAY_CTRL, RESERVED_3_MASK, ENABLE);
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@ -45,9 +45,9 @@ static void setDisplayControl(int ctrl, int disp_state)
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*/
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do {
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cnt++;
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POKE32(PANEL_DISPLAY_CTRL, ulDisplayCtrlReg);
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} while ((PEEK32(PANEL_DISPLAY_CTRL) & ~ulReservedBits) !=
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(ulDisplayCtrlReg & ~ulReservedBits));
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POKE32(PANEL_DISPLAY_CTRL, reg);
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} while ((PEEK32(PANEL_DISPLAY_CTRL) & ~reserved) !=
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(reg & ~reserved));
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printk("Set Panel Plane enbit:after tried %d times\n", cnt);
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} else {
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/* When turning off, there is no rule on the programming
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@ -57,28 +57,28 @@ static void setDisplayControl(int ctrl, int disp_state)
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* next vertical sync. Need to find out if it is necessary to
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* wait for 1 vsync before modifying the timing enable bit.
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* */
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ulDisplayCtrlReg = FIELD_SET(ulDisplayCtrlReg,
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reg = FIELD_SET(reg,
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PANEL_DISPLAY_CTRL, PLANE, DISABLE);
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POKE32(PANEL_DISPLAY_CTRL, ulDisplayCtrlReg);
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POKE32(PANEL_DISPLAY_CTRL, reg);
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ulDisplayCtrlReg = FIELD_SET(ulDisplayCtrlReg,
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reg = FIELD_SET(reg,
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PANEL_DISPLAY_CTRL, TIMING, DISABLE);
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POKE32(PANEL_DISPLAY_CTRL, ulDisplayCtrlReg);
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POKE32(PANEL_DISPLAY_CTRL, reg);
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}
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} else {
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/* Set the secondary display control */
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ulDisplayCtrlReg = PEEK32(CRT_DISPLAY_CTRL);
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reg = PEEK32(CRT_DISPLAY_CTRL);
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if (disp_state) {
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/* Timing should be enabled first before enabling the plane because changing at the
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same time does not guarantee that the plane will also enabled or disabled.
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*/
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ulDisplayCtrlReg = FIELD_SET(ulDisplayCtrlReg,
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reg = FIELD_SET(reg,
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CRT_DISPLAY_CTRL, TIMING, ENABLE);
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POKE32(CRT_DISPLAY_CTRL, ulDisplayCtrlReg);
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POKE32(CRT_DISPLAY_CTRL, reg);
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ulDisplayCtrlReg = FIELD_SET(ulDisplayCtrlReg,
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reg = FIELD_SET(reg,
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CRT_DISPLAY_CTRL, PLANE, ENABLE);
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/* Added some masks to mask out the reserved bits.
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@ -87,16 +87,16 @@ static void setDisplayControl(int ctrl, int disp_state)
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* reserved bits are needed to be masked out.
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*/
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ulReservedBits = FIELD_SET(0, CRT_DISPLAY_CTRL, RESERVED_1_MASK, ENABLE) |
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reserved = FIELD_SET(0, CRT_DISPLAY_CTRL, RESERVED_1_MASK, ENABLE) |
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FIELD_SET(0, CRT_DISPLAY_CTRL, RESERVED_2_MASK, ENABLE) |
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FIELD_SET(0, CRT_DISPLAY_CTRL, RESERVED_3_MASK, ENABLE) |
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FIELD_SET(0, CRT_DISPLAY_CTRL, RESERVED_4_MASK, ENABLE);
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do {
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cnt++;
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POKE32(CRT_DISPLAY_CTRL, ulDisplayCtrlReg);
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} while ((PEEK32(CRT_DISPLAY_CTRL) & ~ulReservedBits) !=
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(ulDisplayCtrlReg & ~ulReservedBits));
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POKE32(CRT_DISPLAY_CTRL, reg);
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} while ((PEEK32(CRT_DISPLAY_CTRL) & ~reserved) !=
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(reg & ~reserved));
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printk("Set Crt Plane enbit:after tried %d times\n", cnt);
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} else {
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/* When turning off, there is no rule on the programming
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@ -106,13 +106,13 @@ static void setDisplayControl(int ctrl, int disp_state)
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* vertical sync. Need to find out if it is necessary to
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* wait for 1 vsync before modifying the timing enable bit.
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*/
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ulDisplayCtrlReg = FIELD_SET(ulDisplayCtrlReg,
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reg = FIELD_SET(reg,
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CRT_DISPLAY_CTRL, PLANE, DISABLE);
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POKE32(CRT_DISPLAY_CTRL, ulDisplayCtrlReg);
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POKE32(CRT_DISPLAY_CTRL, reg);
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ulDisplayCtrlReg = FIELD_SET(ulDisplayCtrlReg,
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reg = FIELD_SET(reg,
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CRT_DISPLAY_CTRL, TIMING, DISABLE);
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POKE32(CRT_DISPLAY_CTRL, ulDisplayCtrlReg);
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POKE32(CRT_DISPLAY_CTRL, reg);
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}
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}
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}
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