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arm64: dts: mt8183: support coresight-cpu-debug for mt8183

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Add coresight-cpu-debug nodes to mt8183 for dumping
EDPRSR, EDPCSR, EDCIDSR, EDVIDSR
while kernel panic happens

Signed-off-by: Seiya Wang <seiya.wang@mediatek.com>
Link: https://lore.kernel.org/r/20211102090230.25013-1-seiya.wang@mediatek.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
This commit is contained in:
Seiya Wang 2021-11-02 17:02:30 +08:00 committed by Matthias Brugger
parent 54337a96f3
commit 7781083fd6
1 changed files with 64 additions and 0 deletions
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64
arch/arm64/boot/dts/mediatek/mt8183.dtsi
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@ -367,6 +367,70 @@ sysirq: interrupt-controller@c530a80 {
reg = <0 0x0c530a80 0 0x50>;
};
cpu_debug0: cpu-debug@d410000 {
compatible = "arm,coresight-cpu-debug", "arm,primecell";
reg = <0x0 0xd410000 0x0 0x1000>;
clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
clock-names = "apb_pclk";
cpu = <&cpu0>;
};
cpu_debug1: cpu-debug@d510000 {
compatible = "arm,coresight-cpu-debug", "arm,primecell";
reg = <0x0 0xd510000 0x0 0x1000>;
clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
clock-names = "apb_pclk";
cpu = <&cpu1>;
};
cpu_debug2: cpu-debug@d610000 {
compatible = "arm,coresight-cpu-debug", "arm,primecell";
reg = <0x0 0xd610000 0x0 0x1000>;
clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
clock-names = "apb_pclk";
cpu = <&cpu2>;
};
cpu_debug3: cpu-debug@d710000 {
compatible = "arm,coresight-cpu-debug", "arm,primecell";
reg = <0x0 0xd710000 0x0 0x1000>;
clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
clock-names = "apb_pclk";
cpu = <&cpu3>;
};
cpu_debug4: cpu-debug@d810000 {
compatible = "arm,coresight-cpu-debug", "arm,primecell";
reg = <0x0 0xd810000 0x0 0x1000>;
clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
clock-names = "apb_pclk";
cpu = <&cpu4>;
};
cpu_debug5: cpu-debug@d910000 {
compatible = "arm,coresight-cpu-debug", "arm,primecell";
reg = <0x0 0xd910000 0x0 0x1000>;
clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
clock-names = "apb_pclk";
cpu = <&cpu5>;
};
cpu_debug6: cpu-debug@da10000 {
compatible = "arm,coresight-cpu-debug", "arm,primecell";
reg = <0x0 0xda10000 0x0 0x1000>;
clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
clock-names = "apb_pclk";
cpu = <&cpu6>;
};
cpu_debug7: cpu-debug@db10000 {
compatible = "arm,coresight-cpu-debug", "arm,primecell";
reg = <0x0 0xdb10000 0x0 0x1000>;
clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
clock-names = "apb_pclk";
cpu = <&cpu7>;
};
topckgen: syscon@10000000 {
compatible = "mediatek,mt8183-topckgen", "syscon";
reg = <0 0x10000000 0 0x1000>;