Merge branch 'x86-uv-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip
* 'x86-uv-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: x86, UV, BAU: Extend for more than 16 cpus per socket x86, UV: Fix the effect of extra bits in the hub nodeid register x86, UV: Add common uv_early_read_mmr() function for reading MMRs
This commit is contained in:
Linus Torvalds
commit
77a0dd54ba
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@ -26,20 +26,22 @@
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* BAU_SB_DESCRIPTOR_BASE register, set 1 is located at BASE + 512,
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* set 2 is at BASE + 2*512, set 3 at BASE + 3*512, and so on.
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*
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* We will use 31 sets, one for sending BAU messages from each of the 32
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* We will use one set for sending BAU messages from each of the
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* cpu's on the uvhub.
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*
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* TLB shootdown will use the first of the 8 descriptors of each set.
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* Each of the descriptors is 64 bytes in size (8*64 = 512 bytes in a set).
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*/
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#define MAX_CPUS_PER_UVHUB 64
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#define MAX_CPUS_PER_SOCKET 32
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#define UV_ADP_SIZE 64 /* hardware-provided max. */
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#define UV_CPUS_PER_ACT_STATUS 32 /* hardware-provided max. */
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#define UV_ITEMS_PER_DESCRIPTOR 8
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/* the 'throttle' to prevent the hardware stay-busy bug */
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#define MAX_BAU_CONCURRENT 3
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#define UV_CPUS_PER_ACT_STATUS 32
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#define UV_ACT_STATUS_MASK 0x3
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#define UV_ACT_STATUS_SIZE 2
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#define UV_ADP_SIZE 32
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#define UV_DISTRIBUTION_SIZE 256
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#define UV_SW_ACK_NPENDING 8
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#define UV_NET_ENDPOINT_INTD 0x38
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@ -100,7 +102,6 @@
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* number of destination side software ack resources
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*/
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#define DEST_NUM_RESOURCES 8
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#define MAX_CPUS_PER_NODE 32
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/*
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* completion statuses for sending a TLB flush message
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*/
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@ -48,6 +48,16 @@ unsigned int uv_apicid_hibits;
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EXPORT_SYMBOL_GPL(uv_apicid_hibits);
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static DEFINE_SPINLOCK(uv_nmi_lock);
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static unsigned long __init uv_early_read_mmr(unsigned long addr)
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{
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unsigned long val, *mmr;
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mmr = early_ioremap(UV_LOCAL_MMR_BASE | addr, sizeof(*mmr));
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val = *mmr;
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early_iounmap(mmr, sizeof(*mmr));
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return val;
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}
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static inline bool is_GRU_range(u64 start, u64 end)
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{
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return start >= gru_start_paddr && end <= gru_end_paddr;
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@ -58,28 +68,24 @@ static bool uv_is_untracked_pat_range(u64 start, u64 end)
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return is_ISA_range(start, end) || is_GRU_range(start, end);
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}
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static int early_get_nodeid(void)
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static int __init early_get_pnodeid(void)
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{
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union uvh_node_id_u node_id;
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unsigned long *mmr;
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mmr = early_ioremap(UV_LOCAL_MMR_BASE | UVH_NODE_ID, sizeof(*mmr));
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node_id.v = *mmr;
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early_iounmap(mmr, sizeof(*mmr));
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union uvh_rh_gam_config_mmr_u m_n_config;
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int pnode;
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/* Currently, all blades have same revision number */
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node_id.v = uv_early_read_mmr(UVH_NODE_ID);
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m_n_config.v = uv_early_read_mmr(UVH_RH_GAM_CONFIG_MMR);
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uv_min_hub_revision_id = node_id.s.revision;
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return node_id.s.node_id;
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pnode = (node_id.s.node_id >> 1) & ((1 << m_n_config.s.n_skt) - 1);
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return pnode;
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}
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static void __init early_get_apic_pnode_shift(void)
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{
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unsigned long *mmr;
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mmr = early_ioremap(UV_LOCAL_MMR_BASE | UVH_APICID, sizeof(*mmr));
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uvh_apicid.v = *mmr;
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early_iounmap(mmr, sizeof(*mmr));
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uvh_apicid.v = uv_early_read_mmr(UVH_APICID);
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if (!uvh_apicid.v)
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/*
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* Old bios, use default value
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@ -95,21 +101,17 @@ static void __init early_get_apic_pnode_shift(void)
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static void __init uv_set_apicid_hibit(void)
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{
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union uvh_lb_target_physical_apic_id_mask_u apicid_mask;
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unsigned long *mmr;
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mmr = early_ioremap(UV_LOCAL_MMR_BASE |
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UVH_LB_TARGET_PHYSICAL_APIC_ID_MASK, sizeof(*mmr));
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apicid_mask.v = *mmr;
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early_iounmap(mmr, sizeof(*mmr));
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apicid_mask.v = uv_early_read_mmr(UVH_LB_TARGET_PHYSICAL_APIC_ID_MASK);
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uv_apicid_hibits = apicid_mask.s.bit_enables & UV_APICID_HIBIT_MASK;
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}
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static int __init uv_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
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{
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int nodeid;
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int pnodeid;
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if (!strcmp(oem_id, "SGI")) {
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nodeid = early_get_nodeid();
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pnodeid = early_get_pnodeid();
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early_get_apic_pnode_shift();
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x86_platform.is_untracked_pat_range = uv_is_untracked_pat_range;
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x86_platform.nmi_init = uv_nmi_init;
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@ -119,7 +121,7 @@ static int __init uv_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
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uv_system_type = UV_X2APIC;
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else if (!strcmp(oem_table_id, "UVH")) {
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__get_cpu_var(x2apic_extra_bits) =
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nodeid << (uvh_apicid.s.pnode_shift - 1);
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pnodeid << uvh_apicid.s.pnode_shift;
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uv_system_type = UV_NON_UNIQUE_APIC;
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uv_set_apicid_hibit();
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return 1;
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@ -682,27 +684,32 @@ void uv_nmi_init(void)
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void __init uv_system_init(void)
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{
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union uvh_rh_gam_config_mmr_u m_n_config;
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union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh;
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union uvh_node_id_u node_id;
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unsigned long gnode_upper, lowmem_redir_base, lowmem_redir_size;
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int bytes, nid, cpu, lcpu, pnode, blade, i, j, m_val, n_val;
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int bytes, nid, cpu, lcpu, pnode, blade, i, j, m_val, n_val, n_io;
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int gnode_extra, max_pnode = 0;
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unsigned long mmr_base, present, paddr;
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unsigned short pnode_mask;
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unsigned short pnode_mask, pnode_io_mask;
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map_low_mmrs();
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m_n_config.v = uv_read_local_mmr(UVH_RH_GAM_CONFIG_MMR );
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m_val = m_n_config.s.m_skt;
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n_val = m_n_config.s.n_skt;
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mmioh.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR);
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n_io = mmioh.s.n_io;
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mmr_base =
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uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) &
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~UV_MMR_ENABLE;
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pnode_mask = (1 << n_val) - 1;
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pnode_io_mask = (1 << n_io) - 1;
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node_id.v = uv_read_local_mmr(UVH_NODE_ID);
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gnode_extra = (node_id.s.node_id & ~((1 << n_val) - 1)) >> 1;
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gnode_upper = ((unsigned long)gnode_extra << m_val);
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printk(KERN_DEBUG "UV: N %d, M %d, gnode_upper 0x%lx, gnode_extra 0x%x\n",
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n_val, m_val, gnode_upper, gnode_extra);
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printk(KERN_INFO "UV: N %d, M %d, N_IO: %d, gnode_upper 0x%lx, gnode_extra 0x%x, pnode_mask 0x%x, pnode_io_mask 0x%x\n",
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n_val, m_val, n_io, gnode_upper, gnode_extra, pnode_mask, pnode_io_mask);
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printk(KERN_DEBUG "UV: global MMR base 0x%lx\n", mmr_base);
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@ -735,7 +742,7 @@ void __init uv_system_init(void)
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for (j = 0; j < 64; j++) {
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if (!test_bit(j, &present))
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continue;
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pnode = (i * 64 + j);
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pnode = (i * 64 + j) & pnode_mask;
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uv_blade_info[blade].pnode = pnode;
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uv_blade_info[blade].nr_possible_cpus = 0;
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uv_blade_info[blade].nr_online_cpus = 0;
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@ -756,6 +763,7 @@ void __init uv_system_init(void)
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/*
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* apic_pnode_shift must be set before calling uv_apicid_to_pnode();
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*/
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uv_cpu_hub_info(cpu)->pnode_mask = pnode_mask;
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uv_cpu_hub_info(cpu)->apic_pnode_shift = uvh_apicid.s.pnode_shift;
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pnode = uv_apicid_to_pnode(apicid);
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blade = boot_pnode_to_blade(pnode);
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@ -772,7 +780,6 @@ void __init uv_system_init(void)
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uv_cpu_hub_info(cpu)->numa_blade_id = blade;
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uv_cpu_hub_info(cpu)->blade_processor_id = lcpu;
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uv_cpu_hub_info(cpu)->pnode = pnode;
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uv_cpu_hub_info(cpu)->pnode_mask = pnode_mask;
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uv_cpu_hub_info(cpu)->gpa_mask = (1UL << (m_val + n_val)) - 1;
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uv_cpu_hub_info(cpu)->gnode_upper = gnode_upper;
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uv_cpu_hub_info(cpu)->gnode_extra = gnode_extra;
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@ -796,7 +803,7 @@ void __init uv_system_init(void)
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map_gru_high(max_pnode);
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map_mmr_high(max_pnode);
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map_mmioh_high(max_pnode);
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map_mmioh_high(max_pnode & pnode_io_mask);
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uv_cpu_init();
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uv_scir_register_cpu_notifier();
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@ -1341,7 +1341,7 @@ uv_activation_descriptor_init(int node, int pnode)
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/*
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* each bau_desc is 64 bytes; there are 8 (UV_ITEMS_PER_DESCRIPTOR)
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* per cpu; and up to 32 (UV_ADP_SIZE) cpu's per uvhub
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* per cpu; and one per cpu on the uvhub (UV_ADP_SIZE)
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*/
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bau_desc = kmalloc_node(sizeof(struct bau_desc) * UV_ADP_SIZE
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* UV_ITEMS_PER_DESCRIPTOR, GFP_KERNEL, node);
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@ -1490,7 +1490,7 @@ calculate_destination_timeout(void)
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/*
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* initialize the bau_control structure for each cpu
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*/
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static void __init uv_init_per_cpu(int nuvhubs)
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static int __init uv_init_per_cpu(int nuvhubs)
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{
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int i;
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int cpu;
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@ -1507,7 +1507,7 @@ static void __init uv_init_per_cpu(int nuvhubs)
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struct bau_control *smaster = NULL;
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struct socket_desc {
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short num_cpus;
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short cpu_number[16];
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short cpu_number[MAX_CPUS_PER_SOCKET];
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};
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struct uvhub_desc {
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unsigned short socket_mask;
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@ -1540,6 +1540,10 @@ static void __init uv_init_per_cpu(int nuvhubs)
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sdp = &bdp->socket[socket];
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sdp->cpu_number[sdp->num_cpus] = cpu;
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sdp->num_cpus++;
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if (sdp->num_cpus > MAX_CPUS_PER_SOCKET) {
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printk(KERN_EMERG "%d cpus per socket invalid\n", sdp->num_cpus);
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return 1;
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}
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}
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for (uvhub = 0; uvhub < nuvhubs; uvhub++) {
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if (!(*(uvhub_mask + (uvhub/8)) & (1 << (uvhub%8))))
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@ -1570,6 +1574,12 @@ static void __init uv_init_per_cpu(int nuvhubs)
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bcp->uvhub_master = hmaster;
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bcp->uvhub_cpu = uv_cpu_hub_info(cpu)->
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blade_processor_id;
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if (bcp->uvhub_cpu >= MAX_CPUS_PER_UVHUB) {
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printk(KERN_EMERG
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"%d cpus per uvhub invalid\n",
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bcp->uvhub_cpu);
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return 1;
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}
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}
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nextsocket:
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socket++;
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@ -1595,6 +1605,7 @@ nextsocket:
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bcp->congested_reps = congested_reps;
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bcp->congested_period = congested_period;
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}
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return 0;
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}
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/*
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@ -1625,7 +1636,10 @@ static int __init uv_bau_init(void)
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spin_lock_init(&disable_lock);
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congested_cycles = microsec_2_cycles(congested_response_us);
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uv_init_per_cpu(nuvhubs);
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if (uv_init_per_cpu(nuvhubs)) {
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nobau = 1;
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return 0;
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}
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uv_partition_base_pnode = 0x7fffffff;
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for (uvhub = 0; uvhub < nuvhubs; uvhub++)
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