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powerpc/perf: Add kernel support for new MSR[HV PR] bits in trace-imc
IMC trace-mode record has MSR[HV PR] bits added in the third DW. These bits can be used to set the cpumode for the instruction pointer captured in each sample. Add support in kernel to use these bits to set the cpumode for each sample. Signed-off-by: Anju T Sudhakar <anju@linux.vnet.ibm.com> Signed-off-by: Madhavan Srinivasan <maddy@linux.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20200713144623.508695-1-maddy@linux.ibm.com
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2 changed files with 29 additions and 5 deletions
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@ -99,6 +99,11 @@ struct trace_imc_data {
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*/
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#define IMC_TRACE_RECORD_TB1_MASK 0x3ffffffffffULL
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/*
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* Bit 0:1 in third DW of IMC trace record
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* specifies the MSR[HV PR] values.
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*/
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#define IMC_TRACE_RECORD_VAL_HVPR(x) ((x) >> 62)
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/*
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* Device tree parser code detects IMC pmu support and
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@ -1288,11 +1288,30 @@ static int trace_imc_prepare_sample(struct trace_imc_data *mem,
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header->size = sizeof(*header) + event->header_size;
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header->misc = 0;
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if (is_kernel_addr(data->ip))
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header->misc |= PERF_RECORD_MISC_KERNEL;
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else
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header->misc |= PERF_RECORD_MISC_USER;
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if (cpu_has_feature(CPU_FTR_ARCH_31)) {
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switch (IMC_TRACE_RECORD_VAL_HVPR(mem->val)) {
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case 0:/* when MSR HV and PR not set in the trace-record */
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header->misc |= PERF_RECORD_MISC_GUEST_KERNEL;
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break;
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case 1: /* MSR HV is 0 and PR is 1 */
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header->misc |= PERF_RECORD_MISC_GUEST_USER;
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break;
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case 2: /* MSR HV is 1 and PR is 0 */
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header->misc |= PERF_RECORD_MISC_HYPERVISOR;
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break;
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case 3: /* MSR HV is 1 and PR is 1 */
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header->misc |= PERF_RECORD_MISC_USER;
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break;
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default:
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pr_info("IMC: Unable to set the flag based on MSR bits\n");
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break;
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}
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} else {
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if (is_kernel_addr(data->ip))
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header->misc |= PERF_RECORD_MISC_KERNEL;
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else
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header->misc |= PERF_RECORD_MISC_USER;
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}
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perf_event_header__init_id(header, data, event);
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return 0;
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