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OMAP3: PM: Prevent hang in prcm_interrupt_handler
There are two scenarios where a race condition could result in a hang in the prcm_interrupt handler. These are: 1). Waiting for PRM_IRQSTATUS_MPU register to clear. Bit 0 of the PRM_IRQSTATUS_MPU register indicates that a wake-up event is pending for the MPU. This bit can only be cleared if the all the wake-up events latched in the various PM_WKST_x registers have been cleared. If a wake-up event occurred during the processing of the prcm interrupt handler, after the corresponding PM_WKST_x register was checked but before the PRM_IRQSTATUS_MPU was cleared, then the CPU would be stuck forever waiting for bit 0 in PRM_IRQSTATUS_MPU to be cleared. 2). Waiting for the PM_WKST_x register to clear. Some power domains have more than one wake-up source. The PM_WKST_x registers indicate the source of a wake-up event and need to be cleared after a wake-up event occurs. When the PM_WKST_x registers are read and before they are cleared, it is possible that another wake-up event could occur causing another bit to be set in one of the PM_WKST_x registers. If this did occur after reading a PM_WKST_x register then the CPU would miss this event and get stuck forever in a loop waiting for that PM_WKST_x register to clear. This patch address the above race conditions that would result in a hang. Signed-off-by: Jon Hunter <jon-hunter@ti.com> Reviewed-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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17d857be64
commit
77da2d910a
1 changed files with 62 additions and 85 deletions
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@ -51,97 +51,74 @@ static void (*_omap_sram_idle)(u32 *addr, int save_state);
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static struct powerdomain *mpu_pwrdm;
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/* PRCM Interrupt Handler for wakeups */
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/*
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* PRCM Interrupt Handler Helper Function
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*
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* The purpose of this function is to clear any wake-up events latched
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* in the PRCM PM_WKST_x registers. It is possible that a wake-up event
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* may occur whilst attempting to clear a PM_WKST_x register and thus
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* set another bit in this register. A while loop is used to ensure
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* that any peripheral wake-up events occurring while attempting to
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* clear the PM_WKST_x are detected and cleared.
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*/
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static void prcm_clear_mod_irqs(s16 module, u8 regs)
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{
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u32 wkst, fclk, iclk;
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u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1;
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u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1;
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u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1;
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wkst = prm_read_mod_reg(module, wkst_off);
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if (wkst) {
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iclk = cm_read_mod_reg(module, iclk_off);
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fclk = cm_read_mod_reg(module, fclk_off);
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while (wkst) {
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cm_set_mod_reg_bits(wkst, module, iclk_off);
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cm_set_mod_reg_bits(wkst, module, fclk_off);
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prm_write_mod_reg(wkst, module, wkst_off);
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wkst = prm_read_mod_reg(module, wkst_off);
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}
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cm_write_mod_reg(iclk, module, iclk_off);
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cm_write_mod_reg(fclk, module, fclk_off);
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}
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}
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/*
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* PRCM Interrupt Handler
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*
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* The PRM_IRQSTATUS_MPU register indicates if there are any pending
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* interrupts from the PRCM for the MPU. These bits must be cleared in
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* order to clear the PRCM interrupt. The PRCM interrupt handler is
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* implemented to simply clear the PRM_IRQSTATUS_MPU in order to clear
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* the PRCM interrupt. Please note that bit 0 of the PRM_IRQSTATUS_MPU
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* register indicates that a wake-up event is pending for the MPU and
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* this bit can only be cleared if the all the wake-up events latched
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* in the various PM_WKST_x registers have been cleared. The interrupt
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* handler is implemented using a do-while loop so that if a wake-up
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* event occurred during the processing of the prcm interrupt handler
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* (setting a bit in the corresponding PM_WKST_x register and thus
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* preventing us from clearing bit 0 of the PRM_IRQSTATUS_MPU register)
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* this would be handled.
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*/
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static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
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{
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u32 wkst, irqstatus_mpu;
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u32 fclk, iclk;
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u32 irqstatus_mpu;
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/* WKUP */
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wkst = prm_read_mod_reg(WKUP_MOD, PM_WKST);
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if (wkst) {
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iclk = cm_read_mod_reg(WKUP_MOD, CM_ICLKEN);
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fclk = cm_read_mod_reg(WKUP_MOD, CM_FCLKEN);
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cm_set_mod_reg_bits(wkst, WKUP_MOD, CM_ICLKEN);
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cm_set_mod_reg_bits(wkst, WKUP_MOD, CM_FCLKEN);
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prm_write_mod_reg(wkst, WKUP_MOD, PM_WKST);
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while (prm_read_mod_reg(WKUP_MOD, PM_WKST))
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cpu_relax();
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cm_write_mod_reg(iclk, WKUP_MOD, CM_ICLKEN);
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cm_write_mod_reg(fclk, WKUP_MOD, CM_FCLKEN);
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}
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/* CORE */
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wkst = prm_read_mod_reg(CORE_MOD, PM_WKST1);
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if (wkst) {
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iclk = cm_read_mod_reg(CORE_MOD, CM_ICLKEN1);
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fclk = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
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cm_set_mod_reg_bits(wkst, CORE_MOD, CM_ICLKEN1);
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cm_set_mod_reg_bits(wkst, CORE_MOD, CM_FCLKEN1);
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prm_write_mod_reg(wkst, CORE_MOD, PM_WKST1);
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while (prm_read_mod_reg(CORE_MOD, PM_WKST1))
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cpu_relax();
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cm_write_mod_reg(iclk, CORE_MOD, CM_ICLKEN1);
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cm_write_mod_reg(fclk, CORE_MOD, CM_FCLKEN1);
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}
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wkst = prm_read_mod_reg(CORE_MOD, OMAP3430ES2_PM_WKST3);
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if (wkst) {
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iclk = cm_read_mod_reg(CORE_MOD, CM_ICLKEN3);
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fclk = cm_read_mod_reg(CORE_MOD, OMAP3430ES2_CM_FCLKEN3);
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cm_set_mod_reg_bits(wkst, CORE_MOD, CM_ICLKEN3);
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cm_set_mod_reg_bits(wkst, CORE_MOD, OMAP3430ES2_CM_FCLKEN3);
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prm_write_mod_reg(wkst, CORE_MOD, OMAP3430ES2_PM_WKST3);
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while (prm_read_mod_reg(CORE_MOD, OMAP3430ES2_PM_WKST3))
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cpu_relax();
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cm_write_mod_reg(iclk, CORE_MOD, CM_ICLKEN3);
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cm_write_mod_reg(fclk, CORE_MOD, OMAP3430ES2_CM_FCLKEN3);
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}
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/* PER */
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wkst = prm_read_mod_reg(OMAP3430_PER_MOD, PM_WKST);
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if (wkst) {
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iclk = cm_read_mod_reg(OMAP3430_PER_MOD, CM_ICLKEN);
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fclk = cm_read_mod_reg(OMAP3430_PER_MOD, CM_FCLKEN);
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cm_set_mod_reg_bits(wkst, OMAP3430_PER_MOD, CM_ICLKEN);
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cm_set_mod_reg_bits(wkst, OMAP3430_PER_MOD, CM_FCLKEN);
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prm_write_mod_reg(wkst, OMAP3430_PER_MOD, PM_WKST);
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while (prm_read_mod_reg(OMAP3430_PER_MOD, PM_WKST))
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cpu_relax();
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cm_write_mod_reg(iclk, OMAP3430_PER_MOD, CM_ICLKEN);
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cm_write_mod_reg(fclk, OMAP3430_PER_MOD, CM_FCLKEN);
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}
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if (omap_rev() > OMAP3430_REV_ES1_0) {
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/* USBHOST */
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wkst = prm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, PM_WKST);
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if (wkst) {
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iclk = cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
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CM_ICLKEN);
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fclk = cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
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CM_FCLKEN);
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cm_set_mod_reg_bits(wkst, OMAP3430ES2_USBHOST_MOD,
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CM_ICLKEN);
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cm_set_mod_reg_bits(wkst, OMAP3430ES2_USBHOST_MOD,
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CM_FCLKEN);
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prm_write_mod_reg(wkst, OMAP3430ES2_USBHOST_MOD,
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PM_WKST);
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while (prm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
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PM_WKST))
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cpu_relax();
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cm_write_mod_reg(iclk, OMAP3430ES2_USBHOST_MOD,
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CM_ICLKEN);
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cm_write_mod_reg(fclk, OMAP3430ES2_USBHOST_MOD,
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CM_FCLKEN);
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do {
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prcm_clear_mod_irqs(WKUP_MOD, 1);
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prcm_clear_mod_irqs(CORE_MOD, 1);
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prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1);
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if (omap_rev() > OMAP3430_REV_ES1_0) {
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prcm_clear_mod_irqs(CORE_MOD, 3);
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prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1);
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}
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}
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irqstatus_mpu = prm_read_mod_reg(OCP_MOD,
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OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
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prm_write_mod_reg(irqstatus_mpu, OCP_MOD,
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OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
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irqstatus_mpu = prm_read_mod_reg(OCP_MOD,
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OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
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prm_write_mod_reg(irqstatus_mpu, OCP_MOD,
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OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
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while (prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET))
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cpu_relax();
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} while (prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET));
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return IRQ_HANDLED;
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}
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