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drm/radeon: consolidate cp hdp flushing code for CIK

Browse source 
It's used in several places so move to a common shared
function.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alex Deucher 2014-01-09 16:18:11 -05:00
parent 8158eb9e32
commit 780f5dddae
1 changed files with 27 additions and 28 deletions
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55
drivers/gpu/drm/radeon/cik.c
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@ -3486,6 +3486,30 @@ int cik_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
return r;
}
/**
* cik_hdp_flush_cp_ring_emit - emit an hdp flush on the cp
*
* @rdev: radeon_device pointer
* @ridx: radeon ring index
*
* Emits an hdp flush on the cp.
*/
static void cik_hdp_flush_cp_ring_emit(struct radeon_device *rdev,
int ridx)
{
struct radeon_ring *ring = &rdev->ring[ridx];
/* We should be using the new WAIT_REG_MEM special op packet here
* but it causes the CP to hang
*/
radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
WRITE_DATA_DST_SEL(0)));
radeon_ring_write(ring, HDP_MEM_COHERENCY_FLUSH_CNTL >> 2);
radeon_ring_write(ring, 0);
radeon_ring_write(ring, 0);
}
/**
* cik_fence_gfx_ring_emit - emit a fence on the gfx ring
*
@ -3512,15 +3536,7 @@ void cik_fence_gfx_ring_emit(struct radeon_device *rdev,
radeon_ring_write(ring, fence->seq);
radeon_ring_write(ring, 0);
/* HDP flush */
/* We should be using the new WAIT_REG_MEM special op packet here
* but it causes the CP to hang
*/
radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
WRITE_DATA_DST_SEL(0)));
radeon_ring_write(ring, HDP_MEM_COHERENCY_FLUSH_CNTL >> 2);
radeon_ring_write(ring, 0);
radeon_ring_write(ring, 0);
cik_hdp_flush_cp_ring_emit(rdev, fence->ring);
}
/**
@ -3550,15 +3566,7 @@ void cik_fence_compute_ring_emit(struct radeon_device *rdev,
radeon_ring_write(ring, fence->seq);
radeon_ring_write(ring, 0);
/* HDP flush */
/* We should be using the new WAIT_REG_MEM special op packet here
* but it causes the CP to hang
*/
radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
WRITE_DATA_DST_SEL(0)));
radeon_ring_write(ring, HDP_MEM_COHERENCY_FLUSH_CNTL >> 2);
radeon_ring_write(ring, 0);
radeon_ring_write(ring, 0);
cik_hdp_flush_cp_ring_emit(rdev, fence->ring);
}
bool cik_semaphore_ring_emit(struct radeon_device *rdev,
@ -5553,16 +5561,7 @@ void cik_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm)
radeon_ring_write(ring, VMID(0));
/* HDP flush */
/* We should be using the WAIT_REG_MEM packet here like in
* cik_fence_ring_emit(), but it causes the CP to hang in this
* context...
*/
radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
WRITE_DATA_DST_SEL(0)));
radeon_ring_write(ring, HDP_MEM_COHERENCY_FLUSH_CNTL >> 2);
radeon_ring_write(ring, 0);
radeon_ring_write(ring, 0);
cik_hdp_flush_cp_ring_emit(rdev, ridx);
/* bits 0-15 are the VM contexts0-15 */
radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));