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MIPS: Sync icache for whole exception vector

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Rather than performing cache flushing for a fixed 0x400 bytes, use the
actual size of the vector in order to ensure we cover all emitted code
on systems that make use of vectored interrupts.

Signed-off-by: Paul Burton <paul.burton@mips.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
Tested-by: Serge Semin <fancer.lancer@gmail.com>
Cc: linux-mips@vger.kernel.org
This commit is contained in:
Paul Burton 2019-04-30 22:53:31 +00:00
parent 172dcd935c
commit 783454e2bc
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1 changed files with 1 additions and 1 deletions
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arch/mips/kernel/traps.c
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@ -2454,7 +2454,7 @@ void __init trap_init(void)
else
set_handler(0x080, &except_vec3_generic, 0x80);
local_flush_icache_range(ebase, ebase + 0x400);
local_flush_icache_range(ebase, ebase + vec_size);
sort_extable(__start___dbe_table, __stop___dbe_table);