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imx device tree changes for 3.9

Browse source 
- Some tweaking and updates on device tree sources
  - Enable imx6q-cpufreq support for device tree boot
  - IMX/MXC onewire driver device tree conversion.  Onewire maintainer
    Evgeniy Polyakov gives his ACK to bless it go via arm-soc tree.
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Merge tag 'imx-dt-3.9' of git://git.linaro.org/people/shawnguo/linux-2.6 into late/dt

From Shawn Guo:
imx device tree changes for 3.9

 - Some tweaking and updates on device tree sources
 - Enable imx6q-cpufreq support for device tree boot
 - IMX/MXC onewire driver device tree conversion.  Onewire maintainer
   Evgeniy Polyakov gives his ACK to bless it go via arm-soc tree.

* tag 'imx-dt-3.9' of git://git.linaro.org/people/shawnguo/linux-2.6: (22 commits)
  ARM: dts: add dtsi for imx6q and imx6dl
  ARM: dts: rename imx6q.dtsi to imx6qdl.dtsi
  ARM: dts: i.MX6: Add regulator delay support
  ARM: dts: Add device tree entry for onewire master on i.MX53
  ARM: i.MX53: Add clocks for i.mx53 onewire master.
  W1: Add device tree support to MXC onewire master.
  ARM: imx: enable imx6q-cpufreq support
  ARM: dts: Add apf51 basic support
  ARM i.MX6: change mxs usbphy clock usage
  ARM: dts: imx6q: Remove silicon version from SDMA firmware
  ARM i.MX53: dts: add oftree for MBa53 baseboard
  ARM i.MX53: add dts for the TQ tqma53 module
  ARM: dts: imx53: pinctrl update
  ARM i.MX51 babbage: Add keypad support
  ARM: dts: imx: Add imx51 KPP entry
  ARM: dts: imx25-karo-tx25: Put status entry in the end
  ARM: mx25pdk: Add device tree support
  ARM: dts: imx: use nodes label in board dts
  ARM: dts: add missing imx dtb targets
  ARM: boot: dts: Add an entry for imx27-pdk.dtb
  ...
This commit is contained in:
Olof Johansson 2013-02-12 15:11:40 -08:00
commit 7839c281ed
33 changed files with 2568 additions and 1892 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

6
Documentation/devicetree/bindings/arm/armadeus.txt Normal file
View file

@ -0,0 +1,6 @@
Armadeus i.MX Platforms Device Tree Bindings
-----------------------------------------------
APF51: i.MX51 based module.
Required root node properties:
- compatible = "armadeus,imx51-apf51", "fsl,imx51";

8
Documentation/devicetree/bindings/arm/fsl.txt
View file

@ -5,6 +5,14 @@ i.MX23 Evaluation Kit
Required root node properties:
- compatible = "fsl,imx23-evk", "fsl,imx23";
i.MX25 Product Development Kit
Required root node properties:
- compatible = "fsl,imx25-pdk", "fsl,imx25";
i.MX27 Product Development Kit
Required root node properties:
- compatible = "fsl,imx27-pdk", "fsl,imx27";
i.MX28 Evaluation Kit
Required root node properties:
- compatible = "fsl,imx28-evk", "fsl,imx28";

1
Documentation/devicetree/bindings/clock/imx5-clock.txt
View file

@ -171,6 +171,7 @@ clocks and IDs.
can_sel 156
can1_serial_gate 157
can1_ipg_gate 158
owire_gate 159
Examples (for mx53):

2
Documentation/devicetree/bindings/clock/imx6q-clock.txt
View file

@ -203,6 +203,8 @@ clocks and IDs.
pcie_ref 188
pcie_ref_125m 189
enet_ref 190
usbphy1_gate 191
usbphy2_gate 192
Examples:

19
Documentation/devicetree/bindings/w1/fsl-imx-owire.txt Normal file
View file

@ -0,0 +1,19 @@
* Freescale i.MX One wire bus master controller
Required properties:
- compatible : should be "fsl,imx21-owire"
- reg : Address and length of the register set for the device
Optional properties:
- clocks : phandle of clock that supplies the module (required if platform
clock bindings use device tree)
Example:
- From imx53.dtsi:
owire: owire@63fa4000 {
compatible = "fsl,imx53-owire", "fsl,imx21-owire";
reg = <0x63fa4000 0x4000>;
clocks = <&clks 159>;
status = "disabled";
};

10
arch/arm/boot/dts/Makefile
View file

@ -79,9 +79,17 @@ dtb-$(CONFIG_ARCH_MVEBU) += armada-370-db.dtb \
armada-370-mirabox.dtb \
armada-xp-db.dtb \
armada-xp-openblocks-ax3-4.dtb
dtb-$(CONFIG_ARCH_MXC) += imx51-babbage.dtb \
dtb-$(CONFIG_ARCH_MXC) += \
imx25-karo-tx25.dtb \
imx25-pdk.dtb \
imx27-apf27.dtb \
imx27-pdk.dtb \
imx31-bug.dtb \
imx51-apf51.dtb \
imx51-babbage.dtb \
imx53-ard.dtb \
imx53-evk.dtb \
imx53-mba53.dtb \
imx53-qsb.dtb \
imx53-smd.dtb \
imx6q-arm2.dtb \

36
arch/arm/boot/dts/imx25-karo-tx25.dts
View file

@ -19,26 +19,18 @@ / {
memory {
reg = <0x80000000 0x02000000 0x90000000 0x02000000>;
};
soc {
aips@43f00000 {
uart1: serial@43f90000 {
status = "okay";
};
};
spba@50000000 {
fec: ethernet@50038000 {
status = "okay";
phy-mode = "rmii";
};
};
emi@80000000 {
nand@bb000000 {
nand-on-flash-bbt;
status = "okay";
};
};
};
};
&uart1 {
status = "okay";
};
&fec {
phy-mode = "rmii";
status = "okay";
};
&nfc {
nand-on-flash-bbt;
status = "okay";
};

36
arch/arm/boot/dts/imx25-pdk.dts Normal file
View file

@ -0,0 +1,36 @@
/*
* Copyright 2013 Freescale Semiconductor, Inc.
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/dts-v1/;
/include/ "imx25.dtsi"
/ {
model = "Freescale i.MX25 Product Development Kit";
compatible = "fsl,imx25-pdk", "fsl,imx25";
memory {
reg = <0x80000000 0x4000000>;
};
};
&uart1 {
status = "okay";
};
&fec {
phy-mode = "rmii";
status = "okay";
};
&nfc {
nand-on-flash-bbt;
status = "okay";
};

2
arch/arm/boot/dts/imx25.dtsi
View file

@ -499,7 +499,7 @@ emi@80000000 {
reg = <0x80000000 0x3b002000>;
ranges;
nand@bb000000 {
nfc: nand@bb000000 {
#address-cells = <1>;
#size-cells = <1>;

82
arch/arm/boot/dts/imx27-apf27.dts
View file

@ -32,58 +32,54 @@ osc26m {
clock-frequency = <0>;
};
};
};
soc {
aipi@10000000 {
serial@1000a000 {
status = "okay";
};
&uart1 {
status = "okay";
};
ethernet@1002b000 {
status = "okay";
};
};
&fec {
status = "okay";
};
nand@d8000000 {
status = "okay";
nand-bus-width = <16>;
nand-ecc-mode = "hw";
nand-on-flash-bbt;
&nfc {
status = "okay";
nand-bus-width = <16>;
nand-ecc-mode = "hw";
nand-on-flash-bbt;
partition@0 {
label = "u-boot";
reg = <0x0 0x100000>;
};
partition@0 {
label = "u-boot";
reg = <0x0 0x100000>;
};
partition@100000 {
label = "env";
reg = <0x100000 0x80000>;
};
partition@100000 {
label = "env";
reg = <0x100000 0x80000>;
};
partition@180000 {
label = "env2";
reg = <0x180000 0x80000>;
};
partition@180000 {
label = "env2";
reg = <0x180000 0x80000>;
};
partition@200000 {
label = "firmware";
reg = <0x200000 0x80000>;
};
partition@200000 {
label = "firmware";
reg = <0x200000 0x80000>;
};
partition@280000 {
label = "dtb";
reg = <0x280000 0x80000>;
};
partition@280000 {
label = "dtb";
reg = <0x280000 0x80000>;
};
partition@300000 {
label = "kernel";
reg = <0x300000 0x500000>;
};
partition@300000 {
label = "kernel";
reg = <0x300000 0x500000>;
};
partition@800000 {
label = "rootfs";
reg = <0x800000 0xf800000>;
};
};
partition@800000 {
label = "rootfs";
reg = <0x800000 0xf800000>;
};
};

28
arch/arm/boot/dts/imx27-3ds.dts → arch/arm/boot/dts/imx27-pdk.dts
View file

@ -13,25 +13,19 @@
/include/ "imx27.dtsi"
/ {
model = "mx27_3ds";
compatible = "freescale,imx27-3ds", "fsl,imx27";
model = "Freescale i.MX27 Product Development Kit";
compatible = "fsl,imx27-pdk", "fsl,imx27";
memory {
reg = <0x0 0x0>;
};
soc {
aipi@10000000 { /* aipi1 */
uart1: serial@1000a000 {
fsl,uart-has-rtscts;
status = "okay";
};
};
aipi@10020000 { /* aipi2 */
ethernet@1002b000 {
status = "okay";
};
};
};
};
&uart1 {
fsl,uart-has-rtscts;
status = "okay";
};
&fec {
status = "okay";
};

14
arch/arm/boot/dts/imx31-bug.dts
View file

@ -19,13 +19,9 @@ / {
memory {
reg = <0x80000000 0x8000000>; /* 128M */
};
soc {
aips@43f00000 { /* AIPS1 */
uart5: serial@43fb4000 {
fsl,uart-has-rtscts;
status = "okay";
};
};
};
};
&uart5 {
fsl,uart-has-rtscts;
status = "okay";
};

52
arch/arm/boot/dts/imx51-apf51.dts Normal file
View file

@ -0,0 +1,52 @@
/*
* Copyright 2012 Armadeus Systems - <support@armadeus.com>
* Copyright 2012 Laurent Cans <laurent.cans@gmail.com>
*
* Based on mx51-babbage.dts
* Copyright 2011 Freescale Semiconductor, Inc.
* Copyright 2011 Linaro Ltd.
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/dts-v1/;
/include/ "imx51.dtsi"
/ {
model = "Armadeus Systems APF51 module";
compatible = "armadeus,imx51-apf51", "fsl,imx51";
memory {
reg = <0x90000000 0x20000000>;
};
clocks {
ckih1 {
clock-frequency = <0>;
};
osc {
clock-frequency = <33554432>;
};
};
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec_2>;
phy-mode = "mii";
phy-reset-gpios = <&gpio3 0 0>;
phy-reset-duration = <1>;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3_2>;
status = "okay";
};

478
arch/arm/boot/dts/imx51-babbage.dts
View file

@ -21,239 +21,20 @@ memory {
reg = <0x90000000 0x20000000>;
};
soc {
display@di0 {
compatible = "fsl,imx-parallel-display";
crtcs = <&ipu 0>;
interface-pix-fmt = "rgb24";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ipu_disp1_1>;
};
display@di0 {
compatible = "fsl,imx-parallel-display";
crtcs = <&ipu 0>;
interface-pix-fmt = "rgb24";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ipu_disp1_1>;
};
display@di1 {
compatible = "fsl,imx-parallel-display";
crtcs = <&ipu 1>;
interface-pix-fmt = "rgb565";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ipu_disp2_1>;
};
aips@70000000 { /* aips-1 */
spba@70000000 {
esdhc@70004000 { /* ESDHC1 */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc1_1>;
fsl,cd-controller;
fsl,wp-controller;
status = "okay";
};
esdhc@70008000 { /* ESDHC2 */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc2_1>;
cd-gpios = <&gpio1 6 0>;
wp-gpios = <&gpio1 5 0>;
status = "okay";
};
uart3: serial@7000c000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3_1>;
fsl,uart-has-rtscts;
status = "okay";
};
ecspi@70010000 { /* ECSPI1 */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1_1>;
fsl,spi-num-chipselects = <2>;
cs-gpios = <&gpio4 24 0>, <&gpio4 25 0>;
status = "okay";
pmic: mc13892@0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,mc13892";
spi-max-frequency = <6000000>;
reg = <0>;
interrupt-parent = <&gpio1>;
interrupts = <8 0x4>;
regulators {
sw1_reg: sw1 {
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <1375000>;
regulator-boot-on;
regulator-always-on;
};
sw2_reg: sw2 {
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1850000>;
regulator-boot-on;
regulator-always-on;
};
sw3_reg: sw3 {
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1850000>;
regulator-boot-on;
regulator-always-on;
};
sw4_reg: sw4 {
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1850000>;
regulator-boot-on;
regulator-always-on;
};
vpll_reg: vpll {
regulator-min-microvolt = <1050000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
vdig_reg: vdig {
regulator-min-microvolt = <1650000>;
regulator-max-microvolt = <1650000>;
regulator-boot-on;
};
vsd_reg: vsd {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3150000>;
};
vusb2_reg: vusb2 {
regulator-min-microvolt = <2400000>;
regulator-max-microvolt = <2775000>;
regulator-boot-on;
regulator-always-on;
};
vvideo_reg: vvideo {
regulator-min-microvolt = <2775000>;
regulator-max-microvolt = <2775000>;
};
vaudio_reg: vaudio {
regulator-min-microvolt = <2300000>;
regulator-max-microvolt = <3000000>;
};
vcam_reg: vcam {
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <3000000>;
};
vgen1_reg: vgen1 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
};
vgen2_reg: vgen2 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3150000>;
regulator-always-on;
};
vgen3_reg: vgen3 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2900000>;
regulator-always-on;
};
};
};
flash: at45db321d@1 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "atmel,at45db321d", "atmel,at45", "atmel,dataflash";
spi-max-frequency = <25000000>;
reg = <1>;
partition@0 {
label = "U-Boot";
reg = <0x0 0x40000>;
read-only;
};
partition@40000 {
label = "Kernel";
reg = <0x40000 0x3c0000>;
};
};
};
ssi2: ssi@70014000 {
fsl,mode = "i2s-slave";
status = "okay";
};
};
iomuxc@73fa8000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
hog {
pinctrl_hog: hoggrp {
fsl,pins = <
694 0x20d5 /* MX51_PAD_GPIO1_0__SD1_CD */
697 0x20d5 /* MX51_PAD_GPIO1_1__SD1_WP */
737 0x100 /* MX51_PAD_GPIO1_5__GPIO1_5 */
740 0x100 /* MX51_PAD_GPIO1_6__GPIO1_6 */
121 0x5 /* MX51_PAD_EIM_A27__GPIO2_21 */
402 0x85 /* MX51_PAD_CSPI1_SS0__GPIO4_24 */
405 0x85 /* MX51_PAD_CSPI1_SS1__GPIO4_25 */
>;
};
};
};
uart1: serial@73fbc000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1_1>;
fsl,uart-has-rtscts;
status = "okay";
};
uart2: serial@73fc0000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2_1>;
status = "okay";
};
};
aips@80000000 { /* aips-2 */
i2c@83fc4000 { /* I2C2 */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2_1>;
status = "okay";
sgtl5000: codec@0a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
clock-frequency = <26000000>;
VDDA-supply = <&vdig_reg>;
VDDIO-supply = <&vvideo_reg>;
};
};
audmux@83fd0000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audmux_1>;
status = "okay";
};
ethernet@83fec000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec_1>;
phy-mode = "mii";
status = "okay";
};
};
display@di1 {
compatible = "fsl,imx-parallel-display";
crtcs = <&ipu 1>;
interface-pix-fmt = "rgb565";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ipu_disp2_1>;
};
gpio-keys {
@ -281,3 +62,236 @@ sound {
mux-ext-port = <3>;
};
};
&esdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc1_1>;
fsl,cd-controller;
fsl,wp-controller;
status = "okay";
};
&esdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc2_1>;
cd-gpios = <&gpio1 6 0>;
wp-gpios = <&gpio1 5 0>;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3_1>;
fsl,uart-has-rtscts;
status = "okay";
};
&ecspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1_1>;
fsl,spi-num-chipselects = <2>;
cs-gpios = <&gpio4 24 0>, <&gpio4 25 0>;
status = "okay";
pmic: mc13892@0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,mc13892";
spi-max-frequency = <6000000>;
reg = <0>;
interrupt-parent = <&gpio1>;
interrupts = <8 0x4>;
regulators {
sw1_reg: sw1 {
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <1375000>;
regulator-boot-on;
regulator-always-on;
};
sw2_reg: sw2 {
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1850000>;
regulator-boot-on;
regulator-always-on;
};
sw3_reg: sw3 {
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1850000>;
regulator-boot-on;
regulator-always-on;
};
sw4_reg: sw4 {
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1850000>;
regulator-boot-on;
regulator-always-on;
};
vpll_reg: vpll {
regulator-min-microvolt = <1050000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
vdig_reg: vdig {
regulator-min-microvolt = <1650000>;
regulator-max-microvolt = <1650000>;
regulator-boot-on;
};
vsd_reg: vsd {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3150000>;
};
vusb2_reg: vusb2 {
regulator-min-microvolt = <2400000>;
regulator-max-microvolt = <2775000>;
regulator-boot-on;
regulator-always-on;
};
vvideo_reg: vvideo {
regulator-min-microvolt = <2775000>;
regulator-max-microvolt = <2775000>;
};
vaudio_reg: vaudio {
regulator-min-microvolt = <2300000>;
regulator-max-microvolt = <3000000>;
};
vcam_reg: vcam {
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <3000000>;
};
vgen1_reg: vgen1 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
};
vgen2_reg: vgen2 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3150000>;
regulator-always-on;
};
vgen3_reg: vgen3 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2900000>;
regulator-always-on;
};
};
};
flash: at45db321d@1 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "atmel,at45db321d", "atmel,at45", "atmel,dataflash";
spi-max-frequency = <25000000>;
reg = <1>;
partition@0 {
label = "U-Boot";
reg = <0x0 0x40000>;
read-only;
};
partition@40000 {
label = "Kernel";
reg = <0x40000 0x3c0000>;
};
};
};
&ssi2 {
fsl,mode = "i2s-slave";
status = "okay";
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
hog {
pinctrl_hog: hoggrp {
fsl,pins = <
694 0x20d5 /* MX51_PAD_GPIO1_0__SD1_CD */
697 0x20d5 /* MX51_PAD_GPIO1_1__SD1_WP */
737 0x100 /* MX51_PAD_GPIO1_5__GPIO1_5 */
740 0x100 /* MX51_PAD_GPIO1_6__GPIO1_6 */
121 0x5 /* MX51_PAD_EIM_A27__GPIO2_21 */
402 0x85 /* MX51_PAD_CSPI1_SS0__GPIO4_24 */
405 0x85 /* MX51_PAD_CSPI1_SS1__GPIO4_25 */
>;
};
};
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1_1>;
fsl,uart-has-rtscts;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2_1>;
status = "okay";
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2_1>;
status = "okay";
sgtl5000: codec@0a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
clock-frequency = <26000000>;
VDDA-supply = <&vdig_reg>;
VDDIO-supply = <&vvideo_reg>;
};
};
&audmux {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audmux_1>;
status = "okay";
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec_1>;
phy-mode = "mii";
status = "okay";
};
&kpp {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_kpp_1>;
linux,keymap = <0x00000067 /* KEY_UP */
0x0001006c /* KEY_DOWN */
0x00020072 /* KEY_VOLUMEDOWN */
0x00030066 /* KEY_HOME */
0x0100006a /* KEY_RIGHT */
0x01010069 /* KEY_LEFT */
0x0102001c /* KEY_ENTER */
0x01030073 /* KEY_VOLUMEUP */
0x02000040 /* KEY_F6 */
0x02010042 /* KEY_F8 */
0x02020043 /* KEY_F9 */
0x02030044 /* KEY_F10 */
0x0300003b /* KEY_F1 */
0x0301003c /* KEY_F2 */
0x0302003d /* KEY_F3 */
0x03030074>; /* KEY_POWER */
status = "okay";
};

53
arch/arm/boot/dts/imx51.dtsi
View file

@ -221,6 +221,14 @@ gpio4: gpio@73f90000 {
#interrupt-cells = <2>;
};
kpp: kpp@73f94000 {
compatible = "fsl,imx51-kpp", "fsl,imx21-kpp";
reg = <0x73f94000 0x4000>;
interrupts = <60>;
clocks = <&clks 0>;
status = "disabled";
};
wdog1: wdog@73f98000 {
compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
reg = <0x73f98000 0x4000>;
@ -273,6 +281,29 @@ pinctrl_fec_1: fecgrp-1 {
260 0x80000000 /* MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK */
>;
};
pinctrl_fec_2: fecgrp-2 {
fsl,pins = <
589 0x80000000 /* MX51_PAD_DI_GP3__FEC_TX_ER */
592 0x80000000 /* MX51_PAD_DI2_PIN4__FEC_CRS */
594 0x80000000 /* MX51_PAD_DI2_PIN2__FEC_MDC */
596 0x80000000 /* MX51_PAD_DI2_PIN3__FEC_MDIO */
598 0x80000000 /* MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 */
602 0x80000000 /* MX51_PAD_DI_GP4__FEC_RDATA2 */
604 0x80000000 /* MX51_PAD_DISP2_DAT0__FEC_RDATA3 */
609 0x80000000 /* MX51_PAD_DISP2_DAT1__FEC_RX_ER */
618 0x80000000 /* MX51_PAD_DISP2_DAT6__FEC_TDATA1 */
623 0x80000000 /* MX51_PAD_DISP2_DAT7__FEC_TDATA2 */
628 0x80000000 /* MX51_PAD_DISP2_DAT8__FEC_TDATA3 */
634 0x80000000 /* MX51_PAD_DISP2_DAT9__FEC_TX_EN */
639 0x80000000 /* MX51_PAD_DISP2_DAT10__FEC_COL */
644 0x80000000 /* MX51_PAD_DISP2_DAT11__FEC_RX_CLK */
649 0x80000000 /* MX51_PAD_DISP2_DAT12__FEC_RX_DV */
653 0x80000000 /* MX51_PAD_DISP2_DAT13__FEC_TX_CLK */
657 0x80000000 /* MX51_PAD_DISP2_DAT14__FEC_RDATA0 */
662 0x80000000 /* MX51_PAD_DISP2_DAT15__FEC_TDATA0 */
>;
};
};
ecspi1 {
@ -409,6 +440,28 @@ pinctrl_uart3_1: uart3grp-1 {
49 0x1c5 /* MX51_PAD_EIM_D24__UART3_CTS */
>;
};
pinctrl_uart3_2: uart3grp-2 {
fsl,pins = <
434 0x1c5 /* MX51_PAD_UART3_RXD__UART3_RXD */
430 0x1c5 /* MX51_PAD_UART3_TXD__UART3_TXD */
>;
};
};
kpp {
pinctrl_kpp_1: kppgrp-1 {
fsl,pins = <
438 0xe0 /* MX51_PAD_KEY_ROW0__KEY_ROW0 */
439 0xe0 /* MX51_PAD_KEY_ROW1__KEY_ROW1 */
440 0xe0 /* MX51_PAD_KEY_ROW2__KEY_ROW2 */
441 0xe0 /* MX51_PAD_KEY_ROW3__KEY_ROW3 */
442 0xe8 /* MX51_PAD_KEY_COL0__KEY_COL0 */
444 0xe8 /* MX51_PAD_KEY_COL1__KEY_COL1 */
446 0xe8 /* MX51_PAD_KEY_COL2__KEY_COL2 */
448 0xe8 /* MX51_PAD_KEY_COL3__KEY_COL3 */
>;
};
};
};

126
arch/arm/boot/dts/imx53-ard.dts
View file

@ -21,72 +21,6 @@ memory {
reg = <0x70000000 0x40000000>;
};
soc {
aips@50000000 { /* AIPS1 */
spba@50000000 {
esdhc@50004000 { /* ESDHC1 */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc1_2>;
cd-gpios = <&gpio1 1 0>;
wp-gpios = <&gpio1 9 0>;
status = "okay";
};
};
iomuxc@53fa8000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
hog {
pinctrl_hog: hoggrp {
fsl,pins = <
1077 0x80000000 /* MX53_PAD_GPIO_1__GPIO1_1 */
1085 0x80000000 /* MX53_PAD_GPIO_9__GPIO1_9 */
486 0x80000000 /* MX53_PAD_EIM_EB3__GPIO2_31 */
739 0x80000000 /* MX53_PAD_GPIO_10__GPIO4_0 */
218 0x80000000 /* MX53_PAD_DISP0_DAT16__GPIO5_10 */
226 0x80000000 /* MX53_PAD_DISP0_DAT17__GPIO5_11 */
233 0x80000000 /* MX53_PAD_DISP0_DAT18__GPIO5_12 */
241 0x80000000 /* MX53_PAD_DISP0_DAT19__GPIO5_13 */
429 0x80000000 /* MX53_PAD_EIM_D16__EMI_WEIM_D_16 */
435 0x80000000 /* MX53_PAD_EIM_D17__EMI_WEIM_D_17 */
441 0x80000000 /* MX53_PAD_EIM_D18__EMI_WEIM_D_18 */
448 0x80000000 /* MX53_PAD_EIM_D19__EMI_WEIM_D_19 */
456 0x80000000 /* MX53_PAD_EIM_D20__EMI_WEIM_D_20 */
464 0x80000000 /* MX53_PAD_EIM_D21__EMI_WEIM_D_21 */
471 0x80000000 /* MX53_PAD_EIM_D22__EMI_WEIM_D_22 */
477 0x80000000 /* MX53_PAD_EIM_D23__EMI_WEIM_D_23 */
492 0x80000000 /* MX53_PAD_EIM_D24__EMI_WEIM_D_24 */
500 0x80000000 /* MX53_PAD_EIM_D25__EMI_WEIM_D_25 */
508 0x80000000 /* MX53_PAD_EIM_D26__EMI_WEIM_D_26 */
516 0x80000000 /* MX53_PAD_EIM_D27__EMI_WEIM_D_27 */
524 0x80000000 /* MX53_PAD_EIM_D28__EMI_WEIM_D_28 */
532 0x80000000 /* MX53_PAD_EIM_D29__EMI_WEIM_D_29 */
540 0x80000000 /* MX53_PAD_EIM_D30__EMI_WEIM_D_30 */
548 0x80000000 /* MX53_PAD_EIM_D31__EMI_WEIM_D_31 */
637 0x80000000 /* MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 */
642 0x80000000 /* MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 */
647 0x80000000 /* MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 */
652 0x80000000 /* MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 */
657 0x80000000 /* MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 */
662 0x80000000 /* MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 */
667 0x80000000 /* MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 */
611 0x80000000 /* MX53_PAD_EIM_OE__EMI_WEIM_OE */
616 0x80000000 /* MX53_PAD_EIM_RW__EMI_WEIM_RW */
607 0x80000000 /* MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 */
>;
};
};
};
uart1: serial@53fbc000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1_2>;
status = "okay";
};
};
};
eim-cs1@f4000000 {
#address-cells = <1>;
#size-cells = <1>;
@ -162,3 +96,63 @@ volume-down {
};
};
};
&esdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc1_2>;
cd-gpios = <&gpio1 1 0>;
wp-gpios = <&gpio1 9 0>;
status = "okay";
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
hog {
pinctrl_hog: hoggrp {
fsl,pins = <
1077 0x80000000 /* MX53_PAD_GPIO_1__GPIO1_1 */
1085 0x80000000 /* MX53_PAD_GPIO_9__GPIO1_9 */
486 0x80000000 /* MX53_PAD_EIM_EB3__GPIO2_31 */
739 0x80000000 /* MX53_PAD_GPIO_10__GPIO4_0 */
218 0x80000000 /* MX53_PAD_DISP0_DAT16__GPIO5_10 */
226 0x80000000 /* MX53_PAD_DISP0_DAT17__GPIO5_11 */
233 0x80000000 /* MX53_PAD_DISP0_DAT18__GPIO5_12 */
241 0x80000000 /* MX53_PAD_DISP0_DAT19__GPIO5_13 */
429 0x80000000 /* MX53_PAD_EIM_D16__EMI_WEIM_D_16 */
435 0x80000000 /* MX53_PAD_EIM_D17__EMI_WEIM_D_17 */
441 0x80000000 /* MX53_PAD_EIM_D18__EMI_WEIM_D_18 */
448 0x80000000 /* MX53_PAD_EIM_D19__EMI_WEIM_D_19 */
456 0x80000000 /* MX53_PAD_EIM_D20__EMI_WEIM_D_20 */
464 0x80000000 /* MX53_PAD_EIM_D21__EMI_WEIM_D_21 */
471 0x80000000 /* MX53_PAD_EIM_D22__EMI_WEIM_D_22 */
477 0x80000000 /* MX53_PAD_EIM_D23__EMI_WEIM_D_23 */
492 0x80000000 /* MX53_PAD_EIM_D24__EMI_WEIM_D_24 */
500 0x80000000 /* MX53_PAD_EIM_D25__EMI_WEIM_D_25 */
508 0x80000000 /* MX53_PAD_EIM_D26__EMI_WEIM_D_26 */
516 0x80000000 /* MX53_PAD_EIM_D27__EMI_WEIM_D_27 */
524 0x80000000 /* MX53_PAD_EIM_D28__EMI_WEIM_D_28 */
532 0x80000000 /* MX53_PAD_EIM_D29__EMI_WEIM_D_29 */
540 0x80000000 /* MX53_PAD_EIM_D30__EMI_WEIM_D_30 */
548 0x80000000 /* MX53_PAD_EIM_D31__EMI_WEIM_D_31 */
637 0x80000000 /* MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 */
642 0x80000000 /* MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 */
647 0x80000000 /* MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 */
652 0x80000000 /* MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 */
657 0x80000000 /* MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 */
662 0x80000000 /* MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 */
667 0x80000000 /* MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 */
611 0x80000000 /* MX53_PAD_EIM_OE__EMI_WEIM_OE */
616 0x80000000 /* MX53_PAD_EIM_RW__EMI_WEIM_RW */
607 0x80000000 /* MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 */
>;
};
};
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1_2>;
status = "okay";
};

194
arch/arm/boot/dts/imx53-evk.dts
View file

@ -21,107 +21,6 @@ memory {
reg = <0x70000000 0x80000000>;
};
soc {
aips@50000000 { /* AIPS1 */
spba@50000000 {
esdhc@50004000 { /* ESDHC1 */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc1_1>;
cd-gpios = <&gpio3 13 0>;
wp-gpios = <&gpio3 14 0>;
status = "okay";
};
ecspi@50010000 { /* ECSPI1 */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1_1>;
fsl,spi-num-chipselects = <2>;
cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>;
status = "okay";
flash: at45db321d@1 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "atmel,at45db321d", "atmel,at45", "atmel,dataflash";
spi-max-frequency = <25000000>;
reg = <1>;
partition@0 {
label = "U-Boot";
reg = <0x0 0x40000>;
read-only;
};
partition@40000 {
label = "Kernel";
reg = <0x40000 0x3c0000>;
};
};
};
esdhc@50020000 { /* ESDHC3 */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc3_1>;
cd-gpios = <&gpio3 11 0>;
wp-gpios = <&gpio3 12 0>;
status = "okay";
};
};
iomuxc@53fa8000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
hog {
pinctrl_hog: hoggrp {
fsl,pins = <
424 0x80000000 /* MX53_PAD_EIM_EB2__GPIO2_30 */
449 0x80000000 /* MX53_PAD_EIM_D19__GPIO3_19 */
693 0x80000000 /* MX53_PAD_EIM_DA11__GPIO3_11 */
697 0x80000000 /* MX53_PAD_EIM_DA12__GPIO3_12 */
701 0x80000000 /* MX53_PAD_EIM_DA13__GPIO3_13 */
705 0x80000000 /* MX53_PAD_EIM_DA14__GPIO3_14 */
868 0x80000000 /* MX53_PAD_PATA_DA_0__GPIO7_6 */
873 0x80000000 /* MX53_PAD_PATA_DA_1__GPIO7_7 */
>;
};
};
};
uart1: serial@53fbc000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1_1>;
status = "okay";
};
};
aips@60000000 { /* AIPS2 */
i2c@63fc4000 { /* I2C2 */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2_1>;
status = "okay";
pmic: mc13892@08 {
compatible = "fsl,mc13892", "fsl,mc13xxx";
reg = <0x08>;
};
codec: sgtl5000@0a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
};
};
ethernet@63fec000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec_1>;
phy-mode = "rmii";
phy-reset-gpios = <&gpio7 6 0>;
status = "okay";
};
};
};
leds {
compatible = "gpio-leds";
@ -132,3 +31,96 @@ green {
};
};
};
&esdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc1_1>;
cd-gpios = <&gpio3 13 0>;
wp-gpios = <&gpio3 14 0>;
status = "okay";
};
&ecspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1_1>;
fsl,spi-num-chipselects = <2>;
cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>;
status = "okay";
flash: at45db321d@1 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "atmel,at45db321d", "atmel,at45", "atmel,dataflash";
spi-max-frequency = <25000000>;
reg = <1>;
partition@0 {
label = "U-Boot";
reg = <0x0 0x40000>;
read-only;
};
partition@40000 {
label = "Kernel";
reg = <0x40000 0x3c0000>;
};
};
};
&esdhc3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc3_1>;
cd-gpios = <&gpio3 11 0>;
wp-gpios = <&gpio3 12 0>;
status = "okay";
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
hog {
pinctrl_hog: hoggrp {
fsl,pins = <
424 0x80000000 /* MX53_PAD_EIM_EB2__GPIO2_30 */
449 0x80000000 /* MX53_PAD_EIM_D19__GPIO3_19 */
693 0x80000000 /* MX53_PAD_EIM_DA11__GPIO3_11 */
697 0x80000000 /* MX53_PAD_EIM_DA12__GPIO3_12 */
701 0x80000000 /* MX53_PAD_EIM_DA13__GPIO3_13 */
705 0x80000000 /* MX53_PAD_EIM_DA14__GPIO3_14 */
868 0x80000000 /* MX53_PAD_PATA_DA_0__GPIO7_6 */
873 0x80000000 /* MX53_PAD_PATA_DA_1__GPIO7_7 */
>;
};
};
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1_1>;
status = "okay";
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2_1>;
status = "okay";
pmic: mc13892@08 {
compatible = "fsl,mc13892", "fsl,mc13xxx";
reg = <0x08>;
};
codec: sgtl5000@0a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
};
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec_1>;
phy-mode = "rmii";
phy-reset-gpios = <&gpio7 6 0>;
status = "okay";
};

130
arch/arm/boot/dts/imx53-mba53.dts Normal file
View file

@ -0,0 +1,130 @@
/*
* Copyright 2012 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
* Copyright 2012 Steffen Trumtrar <s.trumtrar@pengutronix.de>, Pengutronix
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/dts-v1/;
/include/ "imx53-tqma53.dtsi"
/ {
model = "TQ MBa53 starter kit";
compatible = "tq,mba53", "tq,tqma53", "fsl,imx53";
};
&iomuxc {
lvds1 {
pinctrl_lvds1_1: lvds1-grp1 {
fsl,pins = <730 0x10000 /* LVDS0_TX3 */
732 0x10000 /* LVDS0_CLK */
734 0x10000 /* LVDS0_TX2 */
736 0x10000 /* LVDS0_TX1 */
738 0x10000>; /* LVDS0_TX0 */
};
pinctrl_lvds1_2: lvds1-grp2 {
fsl,pins = <720 0x10000 /* LVDS1_TX3 */
722 0x10000 /* LVDS1_TX2 */
724 0x10000 /* LVDS1_CLK */
726 0x10000 /* LVDS1_TX1 */
728 0x10000>; /* LVDS1_TX0 */
};
};
disp1 {
pinctrl_disp1_1: disp1-grp1 {
fsl,pins = <689 0x10000 /* DISP1_DRDY */
482 0x10000 /* DISP1_HSYNC */
489 0x10000 /* DISP1_VSYNC */
684 0x10000 /* DISP1_DAT_0 */
515 0x10000 /* DISP1_DAT_22 */
523 0x10000 /* DISP1_DAT_23 */
543 0x10000 /* DISP1_DAT_21 */
553 0x10000 /* DISP1_DAT_20 */
558 0x10000 /* DISP1_DAT_19 */
564 0x10000 /* DISP1_DAT_18 */
570 0x10000 /* DISP1_DAT_17 */
575 0x10000 /* DISP1_DAT_16 */
580 0x10000 /* DISP1_DAT_15 */
585 0x10000 /* DISP1_DAT_14 */
590 0x10000 /* DISP1_DAT_13 */
595 0x10000 /* DISP1_DAT_12 */
628 0x10000 /* DISP1_DAT_11 */
634 0x10000 /* DISP1_DAT_10 */
639 0x10000 /* DISP1_DAT_9 */
644 0x10000 /* DISP1_DAT_8 */
649 0x10000 /* DISP1_DAT_7 */
654 0x10000 /* DISP1_DAT_6 */
659 0x10000 /* DISP1_DAT_5 */
664 0x10000 /* DISP1_DAT_4 */
669 0x10000 /* DISP1_DAT_3 */
674 0x10000 /* DISP1_DAT_2 */
679 0x10000 /* DISP1_DAT_1 */
684 0x10000>; /* DISP1_DAT_0 */
};
};
};
&cspi {
status = "okay";
};
&i2c2 {
codec: sgtl5000@a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
};
expander: pca9554@20 {
compatible = "pca9554";
reg = <0x20>;
interrupts = <109>;
};
sensor2: lm75@49 {
compatible = "lm75";
reg = <0x49>;
};
};
&fec {
status = "okay";
};
&esdhc2 {
status = "okay";
};
&uart3 {
status = "okay";
};
&ecspi1 {
status = "okay";
};
&uart1 {
status = "okay";
};
&uart2 {
status = "okay";
};
&can1 {
status = "okay";
};
&can2 {
status = "okay";
};
&i2c3 {
status = "okay";
};

380
arch/arm/boot/dts/imx53-qsb.dts
View file

@ -21,200 +21,6 @@ memory {
reg = <0x70000000 0x40000000>;
};
soc {
aips@50000000 { /* AIPS1 */
spba@50000000 {
esdhc@50004000 { /* ESDHC1 */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc1_1>;
cd-gpios = <&gpio3 13 0>;
status = "okay";
};
ssi2: ssi@50014000 {
fsl,mode = "i2s-slave";
status = "okay";
};
esdhc@50020000 { /* ESDHC3 */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc3_1>;
cd-gpios = <&gpio3 11 0>;
wp-gpios = <&gpio3 12 0>;
status = "okay";
};
};
iomuxc@53fa8000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
hog {
pinctrl_hog: hoggrp {
fsl,pins = <
1071 0x80000000 /* MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK */
1141 0x80000000 /* MX53_PAD_GPIO_8__GPIO1_8 */
982 0x80000000 /* MX53_PAD_PATA_DATA14__GPIO2_14 */
989 0x80000000 /* MX53_PAD_PATA_DATA15__GPIO2_15 */
693 0x80000000 /* MX53_PAD_EIM_DA11__GPIO3_11 */
697 0x80000000 /* MX53_PAD_EIM_DA12__GPIO3_12 */
701 0x80000000 /* MX53_PAD_EIM_DA13__GPIO3_13 */
868 0x80000000 /* MX53_PAD_PATA_DA_0__GPIO7_6 */
1149 0x80000000 /* MX53_PAD_GPIO_16__GPIO7_11 */
>;
};
led_pin_gpio7_7: led_gpio7_7@0 {
fsl,pins = <
873 0x80000000 /* MX53_PAD_PATA_DA_1__GPIO7_7 */
>;
};
};
};
uart1: serial@53fbc000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1_1>;
status = "okay";
};
};
aips@60000000 { /* AIPS2 */
i2c@63fc4000 { /* I2C2 */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2_1>;
status = "okay";
sgtl5000: codec@0a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
VDDA-supply = <&reg_3p2v>;
VDDIO-supply = <&reg_3p2v>;
};
};
i2c@63fc8000 { /* I2C1 */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1_1>;
status = "okay";
accelerometer: mma8450@1c {
compatible = "fsl,mma8450";
reg = <0x1c>;
};
pmic: dialog@48 {
compatible = "dlg,da9053-aa", "dlg,da9052";
reg = <0x48>;
interrupt-parent = <&gpio7>;
interrupts = <11 0x8>; /* low-level active IRQ at GPIO7_11 */
regulators {
buck1_reg: buck1 {
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <2075000>;
regulator-always-on;
};
buck2_reg: buck2 {
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <2075000>;
regulator-always-on;
};
buck3_reg: buck3 {
regulator-min-microvolt = <925000>;
regulator-max-microvolt = <2500000>;
regulator-always-on;
};
buck4_reg: buck4 {
regulator-min-microvolt = <925000>;
regulator-max-microvolt = <2500000>;
regulator-always-on;
};
ldo1_reg: ldo1 {
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
ldo2_reg: ldo2 {
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
ldo3_reg: ldo3 {
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
ldo4_reg: ldo4 {
regulator-min-microvolt = <1725000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
ldo5_reg: ldo5 {
regulator-min-microvolt = <1725000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
ldo6_reg: ldo6 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3600000>;
regulator-always-on;
};
ldo7_reg: ldo7 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3600000>;
regulator-always-on;
};
ldo8_reg: ldo8 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3600000>;
regulator-always-on;
};
ldo9_reg: ldo9 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3600000>;
regulator-always-on;
};
ldo10_reg: ldo10 {
regulator-min-microvolt = <1250000>;
regulator-max-microvolt = <3650000>;
regulator-always-on;
};
};
};
};
audmux@63fd0000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audmux_1>;
status = "okay";
};
ethernet@63fec000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec_1>;
phy-mode = "rmii";
phy-reset-gpios = <&gpio7 6 0>;
status = "okay";
};
};
};
gpio-keys {
compatible = "gpio-keys";
@ -276,3 +82,189 @@ sound {
mux-ext-port = <5>;
};
};
&esdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc1_1>;
cd-gpios = <&gpio3 13 0>;
status = "okay";
};
&ssi2 {
fsl,mode = "i2s-slave";
status = "okay";
};
&esdhc3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc3_1>;
cd-gpios = <&gpio3 11 0>;
wp-gpios = <&gpio3 12 0>;
status = "okay";
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
hog {
pinctrl_hog: hoggrp {
fsl,pins = <
1071 0x80000000 /* MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK */
1141 0x80000000 /* MX53_PAD_GPIO_8__GPIO1_8 */
982 0x80000000 /* MX53_PAD_PATA_DATA14__GPIO2_14 */
989 0x80000000 /* MX53_PAD_PATA_DATA15__GPIO2_15 */
693 0x80000000 /* MX53_PAD_EIM_DA11__GPIO3_11 */
697 0x80000000 /* MX53_PAD_EIM_DA12__GPIO3_12 */
701 0x80000000 /* MX53_PAD_EIM_DA13__GPIO3_13 */
868 0x80000000 /* MX53_PAD_PATA_DA_0__GPIO7_6 */
1149 0x80000000 /* MX53_PAD_GPIO_16__GPIO7_11 */
>;
};
led_pin_gpio7_7: led_gpio7_7@0 {
fsl,pins = <
873 0x80000000 /* MX53_PAD_PATA_DA_1__GPIO7_7 */
>;
};
};
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1_1>;
status = "okay";
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2_1>;
status = "okay";
sgtl5000: codec@0a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
VDDA-supply = <&reg_3p2v>;
VDDIO-supply = <&reg_3p2v>;
};
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1_1>;
status = "okay";
accelerometer: mma8450@1c {
compatible = "fsl,mma8450";
reg = <0x1c>;
};
pmic: dialog@48 {
compatible = "dlg,da9053-aa", "dlg,da9052";
reg = <0x48>;
interrupt-parent = <&gpio7>;
interrupts = <11 0x8>; /* low-level active IRQ at GPIO7_11 */
regulators {
buck1_reg: buck1 {
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <2075000>;
regulator-always-on;
};
buck2_reg: buck2 {
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <2075000>;
regulator-always-on;
};
buck3_reg: buck3 {
regulator-min-microvolt = <925000>;
regulator-max-microvolt = <2500000>;
regulator-always-on;
};
buck4_reg: buck4 {
regulator-min-microvolt = <925000>;
regulator-max-microvolt = <2500000>;
regulator-always-on;
};
ldo1_reg: ldo1 {
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
ldo2_reg: ldo2 {
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
ldo3_reg: ldo3 {
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
ldo4_reg: ldo4 {
regulator-min-microvolt = <1725000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
ldo5_reg: ldo5 {
regulator-min-microvolt = <1725000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
ldo6_reg: ldo6 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3600000>;
regulator-always-on;
};
ldo7_reg: ldo7 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3600000>;
regulator-always-on;
};
ldo8_reg: ldo8 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3600000>;
regulator-always-on;
};
ldo9_reg: ldo9 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3600000>;
regulator-always-on;
};
ldo10_reg: ldo10 {
regulator-min-microvolt = <1250000>;
regulator-max-microvolt = <3650000>;
regulator-always-on;
};
};
};
};
&audmux {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audmux_1>;
status = "okay";
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec_1>;
phy-mode = "rmii";
phy-reset-gpios = <&gpio7 6 0>;
status = "okay";
};

294
arch/arm/boot/dts/imx53-smd.dts
View file

@ -21,157 +21,6 @@ memory {
reg = <0x70000000 0x40000000>;
};
soc {
aips@50000000 { /* AIPS1 */
spba@50000000 {
esdhc@50004000 { /* ESDHC1 */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc1_1>;
cd-gpios = <&gpio3 13 0>;
wp-gpios = <&gpio4 11 0>;
status = "okay";
};
esdhc@50008000 { /* ESDHC2 */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc2_1>;
non-removable;
status = "okay";
};
uart3: serial@5000c000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3_1>;
fsl,uart-has-rtscts;
status = "okay";
};
ecspi@50010000 { /* ECSPI1 */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1_1>;
fsl,spi-num-chipselects = <2>;
cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>;
status = "okay";
zigbee: mc1323@0 {
compatible = "fsl,mc1323";
spi-max-frequency = <8000000>;
reg = <0>;
};
flash: m25p32@1 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,m25p32", "st,m25p";
spi-max-frequency = <20000000>;
reg = <1>;
partition@0 {
label = "U-Boot";
reg = <0x0 0x40000>;
read-only;
};
partition@40000 {
label = "Kernel";
reg = <0x40000 0x3c0000>;
};
};
};
esdhc@50020000 { /* ESDHC3 */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc3_1>;
non-removable;
status = "okay";
};
};
iomuxc@53fa8000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
hog {
pinctrl_hog: hoggrp {
fsl,pins = <
982 0x80000000 /* MX53_PAD_PATA_DATA14__GPIO2_14 */
989 0x80000000 /* MX53_PAD_PATA_DATA15__GPIO2_15 */
424 0x80000000 /* MX53_PAD_EIM_EB2__GPIO2_30 */
701 0x80000000 /* MX53_PAD_EIM_DA13__GPIO3_13 */
449 0x80000000 /* MX53_PAD_EIM_D19__GPIO3_19 */
43 0x80000000 /* MX53_PAD_KEY_ROW2__GPIO4_11 */
868 0x80000000 /* MX53_PAD_PATA_DA_0__GPIO7_6 */
>;
};
};
};
uart1: serial@53fbc000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1_1>;
status = "okay";
};
uart2: serial@53fc0000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2_1>;
status = "okay";
};
};
aips@60000000 { /* AIPS2 */
i2c@63fc4000 { /* I2C2 */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2_1>;
status = "okay";
codec: sgtl5000@0a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
};
magnetometer: mag3110@0e {
compatible = "fsl,mag3110";
reg = <0x0e>;
};
touchkey: mpr121@5a {
compatible = "fsl,mpr121";
reg = <0x5a>;
};
};
i2c@63fc8000 { /* I2C1 */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1_1>;
status = "okay";
accelerometer: mma8450@1c {
compatible = "fsl,mma8450";
reg = <0x1c>;
};
camera: ov5642@3c {
compatible = "ovti,ov5642";
reg = <0x3c>;
};
pmic: dialog@48 {
compatible = "dialog,da9053", "dialog,da9052";
reg = <0x48>;
};
};
ethernet@63fec000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec_1>;
phy-mode = "rmii";
phy-reset-gpios = <&gpio7 6 0>;
status = "okay";
};
};
};
gpio-keys {
compatible = "gpio-keys";
@ -188,3 +37,146 @@ volume-down {
};
};
};
&esdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc1_1>;
cd-gpios = <&gpio3 13 0>;
wp-gpios = <&gpio4 11 0>;
status = "okay";
};
&esdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc2_1>;
non-removable;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3_1>;
fsl,uart-has-rtscts;
status = "okay";
};
&ecspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1_1>;
fsl,spi-num-chipselects = <2>;
cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>;
status = "okay";
zigbee: mc1323@0 {
compatible = "fsl,mc1323";
spi-max-frequency = <8000000>;
reg = <0>;
};
flash: m25p32@1 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,m25p32", "st,m25p";
spi-max-frequency = <20000000>;
reg = <1>;
partition@0 {
label = "U-Boot";
reg = <0x0 0x40000>;
read-only;
};
partition@40000 {
label = "Kernel";
reg = <0x40000 0x3c0000>;
};
};
};
&esdhc3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc3_1>;
non-removable;
status = "okay";
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
hog {
pinctrl_hog: hoggrp {
fsl,pins = <
982 0x80000000 /* MX53_PAD_PATA_DATA14__GPIO2_14 */
989 0x80000000 /* MX53_PAD_PATA_DATA15__GPIO2_15 */
424 0x80000000 /* MX53_PAD_EIM_EB2__GPIO2_30 */
701 0x80000000 /* MX53_PAD_EIM_DA13__GPIO3_13 */
449 0x80000000 /* MX53_PAD_EIM_D19__GPIO3_19 */
43 0x80000000 /* MX53_PAD_KEY_ROW2__GPIO4_11 */
868 0x80000000 /* MX53_PAD_PATA_DA_0__GPIO7_6 */
>;
};
};
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1_1>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2_1>;
status = "okay";
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2_1>;
status = "okay";
codec: sgtl5000@0a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
};
magnetometer: mag3110@0e {
compatible = "fsl,mag3110";
reg = <0x0e>;
};
touchkey: mpr121@5a {
compatible = "fsl,mpr121";
reg = <0x5a>;
};
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1_1>;
status = "okay";
accelerometer: mma8450@1c {
compatible = "fsl,mma8450";
reg = <0x1c>;
};
camera: ov5642@3c {
compatible = "ovti,ov5642";
reg = <0x3c>;
};
pmic: dialog@48 {
compatible = "dialog,da9053", "dialog,da9052";
reg = <0x48>;
};
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec_1>;
phy-mode = "rmii";
phy-reset-gpios = <&gpio7 6 0>;
status = "okay";
};

172
arch/arm/boot/dts/imx53-tqma53.dtsi Normal file
View file

@ -0,0 +1,172 @@
/*
* Copyright 2012 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
* Copyright 2012 Steffen Trumtrar <s.trumtrar@pengutronix.de>, Pengutronix
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/include/ "imx53.dtsi"
/ {
model = "TQ TQMa53";
compatible = "tq,tqma53", "fsl,imx53";
memory {
reg = <0x70000000 0x40000000>; /* Up to 1GiB */
};
regulators {
compatible = "simple-bus";
reg_3p3v: 3p3v {
compatible = "regulator-fixed";
regulator-name = "3P3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
};
};
&esdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc2_1>;
wp-gpios = <&gpio1 2 0>;
cd-gpios = <&gpio1 4 0>;
status = "disabled";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3_2>;
status = "disabled";
};
&ecspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1_1>;
fsl,spi-num-chipselects = <4>;
cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>,
<&gpio3 24 0>, <&gpio3 25 0>;
status = "disabled";
};
&esdhc3 { /* EMMC */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc3_1>;
vmmc-supply = <&reg_3p3v>;
non-removable;
bus-width = <8>;
status = "okay";
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
i2s {
pinctrl_i2s_1: i2s-grp1 {
fsl,pins = <
1 0x10000 /* I2S_MCLK */
10 0x10000 /* I2S_SCLK */
17 0x10000 /* I2S_DOUT */
23 0x10000 /* I2S_LRCLK*/
30 0x10000 /* I2S_DIN */
>;
};
};
hog {
pinctrl_hog: hoggrp {
fsl,pins = <
610 0x10000 /* MX53_PAD_EIM_CS1__IPU_DI1_PIN6 (VSYNC)*/
711 0x10000 /* MX53_PAD_EIM_DA15__IPU_DI1_PIN4 (HSYNC)*/
873 0x10000 /* MX53_PAD_PATA_DA_1__GPIO7_7 (LCD_BLT_EN)*/
878 0x10000 /* MX53_PAD_PATA_DA_2__GPIO7_8 (LCD_RESET)*/
922 0x10000 /* MX53_PAD_PATA_DATA5__GPIO2_5 (LCD_POWER)*/
928 0x10000 /* MX53_PAD_PATA_DATA6__GPIO2_6 (PMIC_INT)*/
982 0x10000 /* MX53_PAD_PATA_DATA14__GPIO2_14 (CSI_RST)*/
989 0x10000 /* MX53_PAD_PATA_DATA15__GPIO2_15 (CSI_PWDN)*/
1069 0x10000 /* MX53_PAD_GPIO_0__GPIO1_0 (SYSTEM_DOWN)*/
1093 0x10000 /* MX53_PAD_GPIO_3__GPIO1_3 */
>;
};
};
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1_2>;
fsl,uart-has-rtscts;
status = "disabled";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2_1>;
status = "disabled";
};
&can1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can1_2>;
status = "disabled";
};
&can2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can2_1>;
status = "disabled";
};
&i2c3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3_1>;
status = "disabled";
};
&cspi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_cspi_1>;
fsl,spi-num-chipselects = <3>;
cs-gpios = <&gpio1 18 0>, <&gpio1 19 0>,
<&gpio1 21 0>;
status = "disabled";
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2_1>;
status = "okay";
pmic: mc34708@8 {
compatible = "fsl,mc34708";
reg = <0x8>;
fsl,mc13xxx-uses-rtc;
interrupt-parent = <&gpio2>;
interrupts = <6 8>; /* PDATA_DATA6, low active */
};
sensor1: lm75@48 {
compatible = "lm75";
reg = <0x48>;
};
eeprom: 24c64@50 {
compatible = "at,24c64";
pagesize = <32>;
reg = <0x50>;
};
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec_1>;
phy-mode = "rmii";
status = "disabled";
};

68
arch/arm/boot/dts/imx53.dtsi
View file

@ -274,6 +274,44 @@ pinctrl_fec_1: fecgrp-1 {
};
};
csi {
pinctrl_csi_1: csigrp-1 {
fsl,pins = <
286 0x1d5 /* MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN */
291 0x1d5 /* MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC */
280 0x1d5 /* MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC */
276 0x1d5 /* MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK */
409 0x1d5 /* MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 */
402 0x1d5 /* MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 */
395 0x1d5 /* MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 */
388 0x1d5 /* MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 */
381 0x1d5 /* MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 */
374 0x1d5 /* MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 */
367 0x1d5 /* MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 */
360 0x1d5 /* MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 */
352 0x1d5 /* MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11 */
344 0x1d5 /* MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10 */
336 0x1d5 /* MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9 */
328 0x1d5 /* MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8 */
320 0x1d5 /* MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7 */
312 0x1d5 /* MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6 */
304 0x1d5 /* MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5 */
296 0x1d5 /* MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4 */
276 0x1d5 /* MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK */
>;
};
};
cspi {
pinctrl_cspi_1: cspigrp-1 {
fsl,pins = <
998 0x1d5 /* MX53_PAD_SD1_DATA0__CSPI_MISO */
1008 0x1d5 /* MX53_PAD_SD1_CMD__CSPI_MOSI */
1022 0x1d5 /* MX53_PAD_SD1_CLK__CSPI_SCLK */
>;
};
};
ecspi1 {
pinctrl_ecspi1_1: ecspi1grp-1 {
fsl,pins = <
@ -349,6 +387,13 @@ pinctrl_can1_1: can1grp-1 {
853 0x80000000 /* MX53_PAD_PATA_DIOR__CAN1_RXCAN */
>;
};
pinctrl_can1_2: can1grp-2 {
fsl,pins = <
37 0x80000000 /* MX53_PAD_KEY_COL2__CAN1_TXCAN */
44 0x80000000 /* MX53_PAD_KEY_ROW2__CAN1_RXCAN */
>;
};
};
can2 {
@ -387,6 +432,14 @@ pinctrl_i2c3_1: i2c3grp-1 {
};
};
owire {
pinctrl_owire_1: owiregrp-1 {
fsl,pins = <
1166 0x80000000 /* MX53_PAD_GPIO_18__OWIRE_LINE */
>;
};
};
uart1 {
pinctrl_uart1_1: uart1grp-1 {
fsl,pins = <
@ -421,6 +474,14 @@ pinctrl_uart3_1: uart3grp-1 {
880 0x1c5 /* MX53_PAD_PATA_DA_2__UART3_RTS */
>;
};
pinctrl_uart3_2: uart3grp-2 {
fsl,pins = <
884 0x1c5 /* MX53_PAD_PATA_CS_0__UART3_TXD_MUX */
888 0x1c5 /* MX53_PAD_PATA_CS_1__UART3_RXD_MUX */
>;
};
};
uart4 {
@ -570,6 +631,13 @@ uart5: serial@63f90000 {
status = "disabled";
};
owire: owire@63fa4000 {
compatible = "fsl,imx53-owire", "fsl,imx21-owire";
reg = <0x63fa4000 0x4000>;
clocks = <&clks 159>;
status = "disabled";
};
ecspi2: ecspi@63fac000 {
#address-cells = <1>;
#size-cells = <0>;

59
arch/arm/boot/dts/imx6dl.dtsi Normal file
View file

@ -0,0 +1,59 @@
/*
* Copyright 2013 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
/include/ "imx6qdl.dtsi"
/ {
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
compatible = "arm,cortex-a9";
reg = <0>;
next-level-cache = <&L2>;
};
cpu@1 {
compatible = "arm,cortex-a9";
reg = <1>;
next-level-cache = <&L2>;
};
};
soc {
aips1: aips-bus@02000000 {
pxp: pxp@020f0000 {
reg = <0x020f0000 0x4000>;
interrupts = <0 98 0x04>;
};
epdc: epdc@020f4000 {
reg = <0x020f4000 0x4000>;
interrupts = <0 97 0x04>;
};
lcdif: lcdif@020f8000 {
reg = <0x020f8000 0x4000>;
interrupts = <0 39 0x04>;
};
};
aips2: aips-bus@02100000 {
i2c4: i2c@021f8000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx1-i2c";
reg = <0x021f8000 0x4000>;
interrupts = <0 35 0x04>;
status = "disabled";
};
};
};
};

124
arch/arm/boot/dts/imx6q-arm2.dts
View file

@ -21,71 +21,6 @@ memory {
reg = <0x10000000 0x80000000>;
};
soc {
gpmi-nand@00112000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand_1>;
status = "disabled"; /* gpmi nand conflicts with SD */
};
aips-bus@02000000 { /* AIPS1 */
iomuxc@020e0000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
hog {
pinctrl_hog: hoggrp {
fsl,pins = <
176 0x80000000 /* MX6Q_PAD_EIM_D25__GPIO_3_25 */
>;
};
};
arm2 {
pinctrl_usdhc3_arm2: usdhc3grp-arm2 {
fsl,pins = <
1363 0x80000000 /* MX6Q_PAD_NANDF_CS0__GPIO_6_11 */
1369 0x80000000 /* MX6Q_PAD_NANDF_CS1__GPIO_6_14 */
>;
};
};
};
};
aips-bus@02100000 { /* AIPS2 */
ethernet@02188000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet_2>;
phy-mode = "rgmii";
status = "okay";
};
usdhc@02198000 { /* uSDHC3 */
cd-gpios = <&gpio6 11 0>;
wp-gpios = <&gpio6 14 0>;
vmmc-supply = <&reg_3p3v>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc3_1
&pinctrl_usdhc3_arm2>;
status = "okay";
};
usdhc@0219c000 { /* uSDHC4 */
non-removable;
vmmc-supply = <&reg_3p3v>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc4_1>;
status = "okay";
};
uart4: serial@021f0000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4_1>;
status = "okay";
};
};
};
regulators {
compatible = "simple-bus";
@ -108,3 +43,62 @@ debug-led {
};
};
};
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand_1>;
status = "disabled"; /* gpmi nand conflicts with SD */
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
hog {
pinctrl_hog: hoggrp {
fsl,pins = <
176 0x80000000 /* MX6Q_PAD_EIM_D25__GPIO_3_25 */
>;
};
};
arm2 {
pinctrl_usdhc3_arm2: usdhc3grp-arm2 {
fsl,pins = <
1363 0x80000000 /* MX6Q_PAD_NANDF_CS0__GPIO_6_11 */
1369 0x80000000 /* MX6Q_PAD_NANDF_CS1__GPIO_6_14 */
>;
};
};
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet_2>;
phy-mode = "rgmii";
status = "okay";
};
&usdhc3 {
cd-gpios = <&gpio6 11 0>;
wp-gpios = <&gpio6 14 0>;
vmmc-supply = <&reg_3p3v>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc3_1
&pinctrl_usdhc3_arm2>;
status = "okay";
};
&usdhc4 {
non-removable;
vmmc-supply = <&reg_3p3v>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc4_1>;
status = "okay";
};
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4_1>;
status = "okay";
};

68
arch/arm/boot/dts/imx6q-sabreauto.dts
View file

@ -20,45 +20,39 @@ / {
memory {
reg = <0x10000000 0x80000000>;
};
};
soc {
aips-bus@02000000 { /* AIPS1 */
iomuxc@020e0000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
hog {
pinctrl_hog: hoggrp {
fsl,pins = <
1376 0x80000000 /* MX6Q_PAD_NANDF_CS2__GPIO_6_15 */
13 0x80000000 /* MX6Q_PAD_SD2_DAT2__GPIO_1_13 */
>;
};
};
};
};
aips-bus@02100000 { /* AIPS2 */
uart4: serial@021f0000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4_1>;
status = "okay";
};
ethernet@02188000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet_2>;
phy-mode = "rgmii";
status = "okay";
};
usdhc@02198000 { /* uSDHC3 */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc3_1>;
cd-gpios = <&gpio6 15 0>;
wp-gpios = <&gpio1 13 0>;
status = "okay";
};
hog {
pinctrl_hog: hoggrp {
fsl,pins = <
1376 0x80000000 /* MX6Q_PAD_NANDF_CS2__GPIO_6_15 */
13 0x80000000 /* MX6Q_PAD_SD2_DAT2__GPIO_1_13 */
>;
};
};
};
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4_1>;
status = "okay";
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet_2>;
phy-mode = "rgmii";
status = "okay";
};
&usdhc3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc3_1>;
cd-gpios = <&gpio6 15 0>;
wp-gpios = <&gpio1 13 0>;
status = "okay";
};

216
arch/arm/boot/dts/imx6q-sabrelite.dts
View file

@ -21,118 +21,6 @@ memory {
reg = <0x10000000 0x40000000>;
};
soc {
aips-bus@02000000 { /* AIPS1 */
spba-bus@02000000 {
ecspi@02008000 { /* eCSPI1 */
fsl,spi-num-chipselects = <1>;
cs-gpios = <&gpio3 19 0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1_1>;
status = "okay";
flash: m25p80@0 {
compatible = "sst,sst25vf016b";
spi-max-frequency = <20000000>;
reg = <0>;
};
};
ssi1: ssi@02028000 {
fsl,mode = "i2s-slave";
status = "okay";
};
};
iomuxc@020e0000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
hog {
pinctrl_hog: hoggrp {
fsl,pins = <
1450 0x80000000 /* MX6Q_PAD_NANDF_D6__GPIO_2_6 */
1458 0x80000000 /* MX6Q_PAD_NANDF_D7__GPIO_2_7 */
121 0x80000000 /* MX6Q_PAD_EIM_D19__GPIO_3_19 */
144 0x80000000 /* MX6Q_PAD_EIM_D22__GPIO_3_22 */
152 0x80000000 /* MX6Q_PAD_EIM_D23__GPIO_3_23 */
1262 0x80000000 /* MX6Q_PAD_SD3_DAT5__GPIO_7_0 */
1270 0x1f0b0 /* MX6Q_PAD_SD3_DAT4__GPIO_7_1 */
953 0x80000000 /* MX6Q_PAD_GPIO_0__CCM_CLKO */
>;
};
};
};
};
aips-bus@02100000 { /* AIPS2 */
usb@02184000 { /* USB OTG */
vbus-supply = <&reg_usb_otg_vbus>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg_1>;
disable-over-current;
status = "okay";
};
usb@02184200 { /* USB1 */
status = "okay";
};
ethernet@02188000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet_1>;
phy-mode = "rgmii";
phy-reset-gpios = <&gpio3 23 0>;
status = "okay";
};
usdhc@02198000 { /* uSDHC3 */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc3_2>;
cd-gpios = <&gpio7 0 0>;
wp-gpios = <&gpio7 1 0>;
vmmc-supply = <&reg_3p3v>;
status = "okay";
};
usdhc@0219c000 { /* uSDHC4 */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc4_2>;
cd-gpios = <&gpio2 6 0>;
wp-gpios = <&gpio2 7 0>;
vmmc-supply = <&reg_3p3v>;
status = "okay";
};
audmux@021d8000 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audmux_1>;
};
uart2: serial@021e8000 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2_1>;
};
i2c@021a0000 { /* I2C1 */
status = "okay";
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1_1>;
codec: sgtl5000@0a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
clocks = <&clks 169>;
VDDA-supply = <&reg_2p5v>;
VDDIO-supply = <&reg_3p3v>;
};
};
};
};
regulators {
compatible = "simple-bus";
@ -176,3 +64,107 @@ sound {
mux-ext-port = <4>;
};
};
&ecspi1 {
fsl,spi-num-chipselects = <1>;
cs-gpios = <&gpio3 19 0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1_1>;
status = "okay";
flash: m25p80@0 {
compatible = "sst,sst25vf016b";
spi-max-frequency = <20000000>;
reg = <0>;
};
};
&ssi1 {
fsl,mode = "i2s-slave";
status = "okay";
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
hog {
pinctrl_hog: hoggrp {
fsl,pins = <
1450 0x80000000 /* MX6Q_PAD_NANDF_D6__GPIO_2_6 */
1458 0x80000000 /* MX6Q_PAD_NANDF_D7__GPIO_2_7 */
121 0x80000000 /* MX6Q_PAD_EIM_D19__GPIO_3_19 */
144 0x80000000 /* MX6Q_PAD_EIM_D22__GPIO_3_22 */
152 0x80000000 /* MX6Q_PAD_EIM_D23__GPIO_3_23 */
1262 0x80000000 /* MX6Q_PAD_SD3_DAT5__GPIO_7_0 */
1270 0x1f0b0 /* MX6Q_PAD_SD3_DAT4__GPIO_7_1 */
953 0x80000000 /* MX6Q_PAD_GPIO_0__CCM_CLKO */
>;
};
};
};
&usbotg {
vbus-supply = <&reg_usb_otg_vbus>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg_1>;
disable-over-current;
status = "okay";
};
&usbh1 {
status = "okay";
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet_1>;
phy-mode = "rgmii";
phy-reset-gpios = <&gpio3 23 0>;
status = "okay";
};
&usdhc3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc3_2>;
cd-gpios = <&gpio7 0 0>;
wp-gpios = <&gpio7 1 0>;
vmmc-supply = <&reg_3p3v>;
status = "okay";
};
&usdhc4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc4_2>;
cd-gpios = <&gpio2 6 0>;
wp-gpios = <&gpio2 7 0>;
vmmc-supply = <&reg_3p3v>;
status = "okay";
};
&audmux {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audmux_1>;
};
&uart2 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2_1>;
};
&i2c1 {
status = "okay";
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1_1>;
codec: sgtl5000@0a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
clocks = <&clks 169>;
VDDA-supply = <&reg_2p5v>;
VDDIO-supply = <&reg_3p3v>;
};
};

102
arch/arm/boot/dts/imx6q-sabresd.dts
View file

@ -21,61 +21,6 @@ memory {
reg = <0x10000000 0x40000000>;
};
soc {
aips-bus@02000000 { /* AIPS1 */
spba-bus@02000000 {
uart1: serial@02020000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1_1>;
status = "okay";
};
};
iomuxc@020e0000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
hog {
pinctrl_hog: hoggrp {
fsl,pins = <
1004 0x80000000 /* MX6Q_PAD_GPIO_4__GPIO_1_4 */
1012 0x80000000 /* MX6Q_PAD_GPIO_5__GPIO_1_5 */
1402 0x80000000 /* MX6Q_PAD_NANDF_D0__GPIO_2_0 */
1410 0x80000000 /* MX6Q_PAD_NANDF_D1__GPIO_2_1 */
1418 0x80000000 /* MX6Q_PAD_NANDF_D2__GPIO_2_2 */
1426 0x80000000 /* MX6Q_PAD_NANDF_D3__GPIO_2_3 */
>;
};
};
};
};
aips-bus@02100000 { /* AIPS2 */
ethernet@02188000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet_1>;
phy-mode = "rgmii";
status = "okay";
};
usdhc@02194000 { /* uSDHC2 */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2_1>;
cd-gpios = <&gpio2 2 0>;
wp-gpios = <&gpio2 3 0>;
status = "okay";
};
usdhc@02198000 { /* uSDHC3 */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc3_1>;
cd-gpios = <&gpio2 0 0>;
wp-gpios = <&gpio2 1 0>;
status = "okay";
};
};
};
gpio-keys {
compatible = "gpio-keys";
@ -92,3 +37,50 @@ volume-down {
};
};
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1_1>;
status = "okay";
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
hog {
pinctrl_hog: hoggrp {
fsl,pins = <
1004 0x80000000 /* MX6Q_PAD_GPIO_4__GPIO_1_4 */
1012 0x80000000 /* MX6Q_PAD_GPIO_5__GPIO_1_5 */
1402 0x80000000 /* MX6Q_PAD_NANDF_D0__GPIO_2_0 */
1410 0x80000000 /* MX6Q_PAD_NANDF_D1__GPIO_2_1 */
1418 0x80000000 /* MX6Q_PAD_NANDF_D2__GPIO_2_2 */
1426 0x80000000 /* MX6Q_PAD_NANDF_D3__GPIO_2_3 */
>;
};
};
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet_1>;
phy-mode = "rgmii";
status = "okay";
};
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2_1>;
cd-gpios = <&gpio2 2 0>;
wp-gpios = <&gpio2 3 0>;
status = "okay";
};
&usdhc3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc3_1>;
cd-gpios = <&gpio2 0 0>;
wp-gpios = <&gpio2 1 0>;
status = "okay";
};

796
arch/arm/boot/dts/imx6q.dtsi
View file

@ -1,33 +1,16 @@
/*
* Copyright 2011 Freescale Semiconductor, Inc.
* Copyright 2011 Linaro Ltd.
* Copyright 2013 Freescale Semiconductor, Inc.
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/include/ "skeleton.dtsi"
/include/ "imx6qdl.dtsi"
/ {
aliases {
serial0 = &uart1;
serial1 = &uart2;
serial2 = &uart3;
serial3 = &uart4;
serial4 = &uart5;
gpio0 = &gpio1;
gpio1 = &gpio2;
gpio2 = &gpio3;
gpio3 = &gpio4;
gpio4 = &gpio5;
gpio5 = &gpio6;
gpio6 = &gpio7;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
@ -38,12 +21,19 @@ cpu@0 {
next-level-cache = <&L2>;
operating-points = <
/* kHz uV */
792000 1100000
1200000 1275000
996000 1250000
792000 1150000
396000 950000
198000 850000
>;
clock-latency = <61036>; /* two CLK32 periods */
cpu0-supply = <&reg_cpu>;
clocks = <&clks 104>, <&clks 6>, <&clks 16>,
<&clks 17>, <&clks 170>;
clock-names = "arm", "pll2_pfd2_396m", "step",
"pll1_sw", "pll1_sys";
arm-supply = <&reg_arm>;
pu-supply = <&reg_pu>;
soc-supply = <&reg_soc>;
};
cpu@1 {
@ -65,142 +55,9 @@ cpu@3 {
};
};
intc: interrupt-controller@00a01000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
#address-cells = <1>;
#size-cells = <1>;
interrupt-controller;
reg = <0x00a01000 0x1000>,
<0x00a00100 0x100>;
};
clocks {
#address-cells = <1>;
#size-cells = <0>;
ckil {
compatible = "fsl,imx-ckil", "fixed-clock";
clock-frequency = <32768>;
};
ckih1 {
compatible = "fsl,imx-ckih1", "fixed-clock";
clock-frequency = <0>;
};
osc {
compatible = "fsl,imx-osc", "fixed-clock";
clock-frequency = <24000000>;
};
};
soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
interrupt-parent = <&intc>;
ranges;
dma-apbh@00110000 {
compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
reg = <0x00110000 0x2000>;
clocks = <&clks 106>;
};
nfc: gpmi-nand@00112000 {
compatible = "fsl,imx6q-gpmi-nand";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
reg-names = "gpmi-nand", "bch";
interrupts = <0 13 0x04>, <0 15 0x04>;
interrupt-names = "gpmi-dma", "bch";
clocks = <&clks 152>, <&clks 153>, <&clks 151>,
<&clks 150>, <&clks 149>;
clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
"gpmi_bch_apb", "per1_bch";
fsl,gpmi-dma-channel = <0>;
status = "disabled";
};
timer@00a00600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0x00a00600 0x20>;
interrupts = <1 13 0xf01>;
};
L2: l2-cache@00a02000 {
compatible = "arm,pl310-cache";
reg = <0x00a02000 0x1000>;
interrupts = <0 92 0x04>;
cache-unified;
cache-level = <2>;
};
aips-bus@02000000 { /* AIPS1 */
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x02000000 0x100000>;
ranges;
spba-bus@02000000 {
compatible = "fsl,spba-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x02000000 0x40000>;
ranges;
spdif: spdif@02004000 {
reg = <0x02004000 0x4000>;
interrupts = <0 52 0x04>;
};
ecspi1: ecspi@02008000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
reg = <0x02008000 0x4000>;
interrupts = <0 31 0x04>;
clocks = <&clks 112>, <&clks 112>;
clock-names = "ipg", "per";
status = "disabled";
};
ecspi2: ecspi@0200c000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
reg = <0x0200c000 0x4000>;
interrupts = <0 32 0x04>;
clocks = <&clks 113>, <&clks 113>;
clock-names = "ipg", "per";
status = "disabled";
};
ecspi3: ecspi@02010000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
reg = <0x02010000 0x4000>;
interrupts = <0 33 0x04>;
clocks = <&clks 114>, <&clks 114>;
clock-names = "ipg", "per";
status = "disabled";
};
ecspi4: ecspi@02014000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
reg = <0x02014000 0x4000>;
interrupts = <0 34 0x04>;
clocks = <&clks 115>, <&clks 115>;
clock-names = "ipg", "per";
status = "disabled";
};
ecspi5: ecspi@02018000 {
#address-cells = <1>;
#size-cells = <0>;
@ -211,361 +68,6 @@ ecspi5: ecspi@02018000 {
clock-names = "ipg", "per";
status = "disabled";
};
uart1: serial@02020000 {
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
reg = <0x02020000 0x4000>;
interrupts = <0 26 0x04>;
clocks = <&clks 160>, <&clks 161>;
clock-names = "ipg", "per";
status = "disabled";
};
esai: esai@02024000 {
reg = <0x02024000 0x4000>;
interrupts = <0 51 0x04>;
};
ssi1: ssi@02028000 {
compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
reg = <0x02028000 0x4000>;
interrupts = <0 46 0x04>;
clocks = <&clks 178>;
fsl,fifo-depth = <15>;
fsl,ssi-dma-events = <38 37>;
status = "disabled";
};
ssi2: ssi@0202c000 {
compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
reg = <0x0202c000 0x4000>;
interrupts = <0 47 0x04>;
clocks = <&clks 179>;
fsl,fifo-depth = <15>;
fsl,ssi-dma-events = <42 41>;
status = "disabled";
};
ssi3: ssi@02030000 {
compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
reg = <0x02030000 0x4000>;
interrupts = <0 48 0x04>;
clocks = <&clks 180>;
fsl,fifo-depth = <15>;
fsl,ssi-dma-events = <46 45>;
status = "disabled";
};
asrc: asrc@02034000 {
reg = <0x02034000 0x4000>;
interrupts = <0 50 0x04>;
};
spba@0203c000 {
reg = <0x0203c000 0x4000>;
};
};
vpu: vpu@02040000 {
reg = <0x02040000 0x3c000>;
interrupts = <0 3 0x04 0 12 0x04>;
};
aipstz@0207c000 { /* AIPSTZ1 */
reg = <0x0207c000 0x4000>;
};
pwm1: pwm@02080000 {
#pwm-cells = <2>;
compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
reg = <0x02080000 0x4000>;
interrupts = <0 83 0x04>;
clocks = <&clks 62>, <&clks 145>;
clock-names = "ipg", "per";
};
pwm2: pwm@02084000 {
#pwm-cells = <2>;
compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
reg = <0x02084000 0x4000>;
interrupts = <0 84 0x04>;
clocks = <&clks 62>, <&clks 146>;
clock-names = "ipg", "per";
};
pwm3: pwm@02088000 {
#pwm-cells = <2>;
compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
reg = <0x02088000 0x4000>;
interrupts = <0 85 0x04>;
clocks = <&clks 62>, <&clks 147>;
clock-names = "ipg", "per";
};
pwm4: pwm@0208c000 {
#pwm-cells = <2>;
compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
reg = <0x0208c000 0x4000>;
interrupts = <0 86 0x04>;
clocks = <&clks 62>, <&clks 148>;
clock-names = "ipg", "per";
};
can1: flexcan@02090000 {
reg = <0x02090000 0x4000>;
interrupts = <0 110 0x04>;
};
can2: flexcan@02094000 {
reg = <0x02094000 0x4000>;
interrupts = <0 111 0x04>;
};
gpt: gpt@02098000 {
compatible = "fsl,imx6q-gpt";
reg = <0x02098000 0x4000>;
interrupts = <0 55 0x04>;
};
gpio1: gpio@0209c000 {
compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
reg = <0x0209c000 0x4000>;
interrupts = <0 66 0x04 0 67 0x04>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio2: gpio@020a0000 {
compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
reg = <0x020a0000 0x4000>;
interrupts = <0 68 0x04 0 69 0x04>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio3: gpio@020a4000 {
compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
reg = <0x020a4000 0x4000>;
interrupts = <0 70 0x04 0 71 0x04>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio4: gpio@020a8000 {
compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
reg = <0x020a8000 0x4000>;
interrupts = <0 72 0x04 0 73 0x04>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio5: gpio@020ac000 {
compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
reg = <0x020ac000 0x4000>;
interrupts = <0 74 0x04 0 75 0x04>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio6: gpio@020b0000 {
compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
reg = <0x020b0000 0x4000>;
interrupts = <0 76 0x04 0 77 0x04>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio7: gpio@020b4000 {
compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
reg = <0x020b4000 0x4000>;
interrupts = <0 78 0x04 0 79 0x04>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
kpp: kpp@020b8000 {
reg = <0x020b8000 0x4000>;
interrupts = <0 82 0x04>;
};
wdog1: wdog@020bc000 {
compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
reg = <0x020bc000 0x4000>;
interrupts = <0 80 0x04>;
clocks = <&clks 0>;
};
wdog2: wdog@020c0000 {
compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
reg = <0x020c0000 0x4000>;
interrupts = <0 81 0x04>;
clocks = <&clks 0>;
status = "disabled";
};
clks: ccm@020c4000 {
compatible = "fsl,imx6q-ccm";
reg = <0x020c4000 0x4000>;
interrupts = <0 87 0x04 0 88 0x04>;
#clock-cells = <1>;
};
anatop: anatop@020c8000 {
compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
reg = <0x020c8000 0x1000>;
interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>;
regulator-1p1@110 {
compatible = "fsl,anatop-regulator";
regulator-name = "vdd1p1";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1375000>;
regulator-always-on;
anatop-reg-offset = <0x110>;
anatop-vol-bit-shift = <8>;
anatop-vol-bit-width = <5>;
anatop-min-bit-val = <4>;
anatop-min-voltage = <800000>;
anatop-max-voltage = <1375000>;
};
regulator-3p0@120 {
compatible = "fsl,anatop-regulator";
regulator-name = "vdd3p0";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <3150000>;
regulator-always-on;
anatop-reg-offset = <0x120>;
anatop-vol-bit-shift = <8>;
anatop-vol-bit-width = <5>;
anatop-min-bit-val = <0>;
anatop-min-voltage = <2625000>;
anatop-max-voltage = <3400000>;
};
regulator-2p5@130 {
compatible = "fsl,anatop-regulator";
regulator-name = "vdd2p5";
regulator-min-microvolt = <2000000>;
regulator-max-microvolt = <2750000>;
regulator-always-on;
anatop-reg-offset = <0x130>;
anatop-vol-bit-shift = <8>;
anatop-vol-bit-width = <5>;
anatop-min-bit-val = <0>;
anatop-min-voltage = <2000000>;
anatop-max-voltage = <2750000>;
};
reg_cpu: regulator-vddcore@140 {
compatible = "fsl,anatop-regulator";
regulator-name = "cpu";
regulator-min-microvolt = <725000>;
regulator-max-microvolt = <1450000>;
regulator-always-on;
anatop-reg-offset = <0x140>;
anatop-vol-bit-shift = <0>;
anatop-vol-bit-width = <5>;
anatop-min-bit-val = <1>;
anatop-min-voltage = <725000>;
anatop-max-voltage = <1450000>;
};
regulator-vddpu@140 {
compatible = "fsl,anatop-regulator";
regulator-name = "vddpu";
regulator-min-microvolt = <725000>;
regulator-max-microvolt = <1450000>;
regulator-always-on;
anatop-reg-offset = <0x140>;
anatop-vol-bit-shift = <9>;
anatop-vol-bit-width = <5>;
anatop-min-bit-val = <1>;
anatop-min-voltage = <725000>;
anatop-max-voltage = <1450000>;
};
regulator-vddsoc@140 {
compatible = "fsl,anatop-regulator";
regulator-name = "vddsoc";
regulator-min-microvolt = <725000>;
regulator-max-microvolt = <1450000>;
regulator-always-on;
anatop-reg-offset = <0x140>;
anatop-vol-bit-shift = <18>;
anatop-vol-bit-width = <5>;
anatop-min-bit-val = <1>;
anatop-min-voltage = <725000>;
anatop-max-voltage = <1450000>;
};
};
usbphy1: usbphy@020c9000 {
compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
reg = <0x020c9000 0x1000>;
interrupts = <0 44 0x04>;
clocks = <&clks 182>;
};
usbphy2: usbphy@020ca000 {
compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
reg = <0x020ca000 0x1000>;
interrupts = <0 45 0x04>;
clocks = <&clks 183>;
};
snvs@020cc000 {
compatible = "fsl,sec-v4.0-mon", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x020cc000 0x4000>;
snvs-rtc-lp@34 {
compatible = "fsl,sec-v4.0-mon-rtc-lp";
reg = <0x34 0x58>;
interrupts = <0 19 0x04 0 20 0x04>;
};
};
epit1: epit@020d0000 { /* EPIT1 */
reg = <0x020d0000 0x4000>;
interrupts = <0 56 0x04>;
};
epit2: epit@020d4000 { /* EPIT2 */
reg = <0x020d4000 0x4000>;
interrupts = <0 57 0x04>;
};
src: src@020d8000 {
compatible = "fsl,imx6q-src";
reg = <0x020d8000 0x4000>;
interrupts = <0 91 0x04 0 96 0x04>;
};
gpc: gpc@020dc000 {
compatible = "fsl,imx6q-gpc";
reg = <0x020dc000 0x4000>;
interrupts = <0 89 0x04 0 90 0x04>;
};
gpr: iomuxc-gpr@020e0000 {
compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
reg = <0x020e0000 0x38>;
};
iomuxc: iomuxc@020e0000 {
@ -780,272 +282,6 @@ pinctrl_usdhc4_2: usdhc4grp-2 {
};
};
};
dcic1: dcic@020e4000 {
reg = <0x020e4000 0x4000>;
interrupts = <0 124 0x04>;
};
dcic2: dcic@020e8000 {
reg = <0x020e8000 0x4000>;
interrupts = <0 125 0x04>;
};
sdma: sdma@020ec000 {
compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
reg = <0x020ec000 0x4000>;
interrupts = <0 2 0x04>;
clocks = <&clks 155>, <&clks 155>;
clock-names = "ipg", "ahb";
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q-to1.bin";
};
};
aips-bus@02100000 { /* AIPS2 */
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x02100000 0x100000>;
ranges;
caam@02100000 {
reg = <0x02100000 0x40000>;
interrupts = <0 105 0x04 0 106 0x04>;
};
aipstz@0217c000 { /* AIPSTZ2 */
reg = <0x0217c000 0x4000>;
};
usbotg: usb@02184000 {
compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
reg = <0x02184000 0x200>;
interrupts = <0 43 0x04>;
clocks = <&clks 162>;
fsl,usbphy = <&usbphy1>;
fsl,usbmisc = <&usbmisc 0>;
status = "disabled";
};
usbh1: usb@02184200 {
compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
reg = <0x02184200 0x200>;
interrupts = <0 40 0x04>;
clocks = <&clks 162>;
fsl,usbphy = <&usbphy2>;
fsl,usbmisc = <&usbmisc 1>;
status = "disabled";
};
usbh2: usb@02184400 {
compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
reg = <0x02184400 0x200>;
interrupts = <0 41 0x04>;
clocks = <&clks 162>;
fsl,usbmisc = <&usbmisc 2>;
status = "disabled";
};
usbh3: usb@02184600 {
compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
reg = <0x02184600 0x200>;
interrupts = <0 42 0x04>;
clocks = <&clks 162>;
fsl,usbmisc = <&usbmisc 3>;
status = "disabled";
};
usbmisc: usbmisc: usbmisc@02184800 {
#index-cells = <1>;
compatible = "fsl,imx6q-usbmisc";
reg = <0x02184800 0x200>;
clocks = <&clks 162>;
};
fec: ethernet@02188000 {
compatible = "fsl,imx6q-fec";
reg = <0x02188000 0x4000>;
interrupts = <0 118 0x04 0 119 0x04>;
clocks = <&clks 117>, <&clks 117>, <&clks 177>;
clock-names = "ipg", "ahb", "ptp";
status = "disabled";
};
mlb@0218c000 {
reg = <0x0218c000 0x4000>;
interrupts = <0 53 0x04 0 117 0x04 0 126 0x04>;
};
usdhc1: usdhc@02190000 {
compatible = "fsl,imx6q-usdhc";
reg = <0x02190000 0x4000>;
interrupts = <0 22 0x04>;
clocks = <&clks 163>, <&clks 163>, <&clks 163>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
status = "disabled";
};
usdhc2: usdhc@02194000 {
compatible = "fsl,imx6q-usdhc";
reg = <0x02194000 0x4000>;
interrupts = <0 23 0x04>;
clocks = <&clks 164>, <&clks 164>, <&clks 164>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
status = "disabled";
};
usdhc3: usdhc@02198000 {
compatible = "fsl,imx6q-usdhc";
reg = <0x02198000 0x4000>;
interrupts = <0 24 0x04>;
clocks = <&clks 165>, <&clks 165>, <&clks 165>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
status = "disabled";
};
usdhc4: usdhc@0219c000 {
compatible = "fsl,imx6q-usdhc";
reg = <0x0219c000 0x4000>;
interrupts = <0 25 0x04>;
clocks = <&clks 166>, <&clks 166>, <&clks 166>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
status = "disabled";
};
i2c1: i2c@021a0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
reg = <0x021a0000 0x4000>;
interrupts = <0 36 0x04>;
clocks = <&clks 125>;
status = "disabled";
};
i2c2: i2c@021a4000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
reg = <0x021a4000 0x4000>;
interrupts = <0 37 0x04>;
clocks = <&clks 126>;
status = "disabled";
};
i2c3: i2c@021a8000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
reg = <0x021a8000 0x4000>;
interrupts = <0 38 0x04>;
clocks = <&clks 127>;
status = "disabled";
};
romcp@021ac000 {
reg = <0x021ac000 0x4000>;
};
mmdc0: mmdc@021b0000 { /* MMDC0 */
compatible = "fsl,imx6q-mmdc";
reg = <0x021b0000 0x4000>;
};
mmdc1: mmdc@021b4000 { /* MMDC1 */
reg = <0x021b4000 0x4000>;
};
weim@021b8000 {
reg = <0x021b8000 0x4000>;
interrupts = <0 14 0x04>;
};
ocotp@021bc000 {
reg = <0x021bc000 0x4000>;
};
ocotp@021c0000 {
reg = <0x021c0000 0x4000>;
interrupts = <0 21 0x04>;
};
tzasc@021d0000 { /* TZASC1 */
reg = <0x021d0000 0x4000>;
interrupts = <0 108 0x04>;
};
tzasc@021d4000 { /* TZASC2 */
reg = <0x021d4000 0x4000>;
interrupts = <0 109 0x04>;
};
audmux: audmux@021d8000 {
compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
reg = <0x021d8000 0x4000>;
status = "disabled";
};
mipi@021dc000 { /* MIPI-CSI */
reg = <0x021dc000 0x4000>;
};
mipi@021e0000 { /* MIPI-DSI */
reg = <0x021e0000 0x4000>;
};
vdoa@021e4000 {
reg = <0x021e4000 0x4000>;
interrupts = <0 18 0x04>;
};
uart2: serial@021e8000 {
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
reg = <0x021e8000 0x4000>;
interrupts = <0 27 0x04>;
clocks = <&clks 160>, <&clks 161>;
clock-names = "ipg", "per";
status = "disabled";
};
uart3: serial@021ec000 {
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
reg = <0x021ec000 0x4000>;
interrupts = <0 28 0x04>;
clocks = <&clks 160>, <&clks 161>;
clock-names = "ipg", "per";
status = "disabled";
};
uart4: serial@021f0000 {
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
reg = <0x021f0000 0x4000>;
interrupts = <0 29 0x04>;
clocks = <&clks 160>, <&clks 161>;
clock-names = "ipg", "per";
status = "disabled";
};
uart5: serial@021f4000 {
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
reg = <0x021f4000 0x4000>;
interrupts = <0 30 0x04>;
clocks = <&clks 160>, <&clks 161>;
clock-names = "ipg", "per";
status = "disabled";
};
};
ipu1: ipu@02400000 {
#crtc-cells = <1>;
compatible = "fsl,imx6q-ipu";
reg = <0x02400000 0x400000>;
interrupts = <0 6 0x4 0 5 0x4>;
clocks = <&clks 130>, <&clks 131>, <&clks 132>;
clock-names = "bus", "di0", "di1";
};
ipu2: ipu@02800000 {

800
arch/arm/boot/dts/imx6qdl.dtsi Normal file
View file

@ -0,0 +1,800 @@
/*
* Copyright 2011 Freescale Semiconductor, Inc.
* Copyright 2011 Linaro Ltd.
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/include/ "skeleton.dtsi"
/ {
aliases {
serial0 = &uart1;
serial1 = &uart2;
serial2 = &uart3;
serial3 = &uart4;
serial4 = &uart5;
gpio0 = &gpio1;
gpio1 = &gpio2;
gpio2 = &gpio3;
gpio3 = &gpio4;
gpio4 = &gpio5;
gpio5 = &gpio6;
gpio6 = &gpio7;
};
intc: interrupt-controller@00a01000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
#address-cells = <1>;
#size-cells = <1>;
interrupt-controller;
reg = <0x00a01000 0x1000>,
<0x00a00100 0x100>;
};
clocks {
#address-cells = <1>;
#size-cells = <0>;
ckil {
compatible = "fsl,imx-ckil", "fixed-clock";
clock-frequency = <32768>;
};
ckih1 {
compatible = "fsl,imx-ckih1", "fixed-clock";
clock-frequency = <0>;
};
osc {
compatible = "fsl,imx-osc", "fixed-clock";
clock-frequency = <24000000>;
};
};
soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
interrupt-parent = <&intc>;
ranges;
dma-apbh@00110000 {
compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
reg = <0x00110000 0x2000>;
clocks = <&clks 106>;
};
gpmi: gpmi-nand@00112000 {
compatible = "fsl,imx6q-gpmi-nand";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
reg-names = "gpmi-nand", "bch";
interrupts = <0 13 0x04>, <0 15 0x04>;
interrupt-names = "gpmi-dma", "bch";
clocks = <&clks 152>, <&clks 153>, <&clks 151>,
<&clks 150>, <&clks 149>;
clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
"gpmi_bch_apb", "per1_bch";
fsl,gpmi-dma-channel = <0>;
status = "disabled";
};
timer@00a00600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0x00a00600 0x20>;
interrupts = <1 13 0xf01>;
};
L2: l2-cache@00a02000 {
compatible = "arm,pl310-cache";
reg = <0x00a02000 0x1000>;
interrupts = <0 92 0x04>;
cache-unified;
cache-level = <2>;
};
aips-bus@02000000 { /* AIPS1 */
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x02000000 0x100000>;
ranges;
spba-bus@02000000 {
compatible = "fsl,spba-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x02000000 0x40000>;
ranges;
spdif: spdif@02004000 {
reg = <0x02004000 0x4000>;
interrupts = <0 52 0x04>;
};
ecspi1: ecspi@02008000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
reg = <0x02008000 0x4000>;
interrupts = <0 31 0x04>;
clocks = <&clks 112>, <&clks 112>;
clock-names = "ipg", "per";
status = "disabled";
};
ecspi2: ecspi@0200c000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
reg = <0x0200c000 0x4000>;
interrupts = <0 32 0x04>;
clocks = <&clks 113>, <&clks 113>;
clock-names = "ipg", "per";
status = "disabled";
};
ecspi3: ecspi@02010000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
reg = <0x02010000 0x4000>;
interrupts = <0 33 0x04>;
clocks = <&clks 114>, <&clks 114>;
clock-names = "ipg", "per";
status = "disabled";
};
ecspi4: ecspi@02014000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
reg = <0x02014000 0x4000>;
interrupts = <0 34 0x04>;
clocks = <&clks 115>, <&clks 115>;
clock-names = "ipg", "per";
status = "disabled";
};
uart1: serial@02020000 {
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
reg = <0x02020000 0x4000>;
interrupts = <0 26 0x04>;
clocks = <&clks 160>, <&clks 161>;
clock-names = "ipg", "per";
status = "disabled";
};
esai: esai@02024000 {
reg = <0x02024000 0x4000>;
interrupts = <0 51 0x04>;
};
ssi1: ssi@02028000 {
compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
reg = <0x02028000 0x4000>;
interrupts = <0 46 0x04>;
clocks = <&clks 178>;
fsl,fifo-depth = <15>;
fsl,ssi-dma-events = <38 37>;
status = "disabled";
};
ssi2: ssi@0202c000 {
compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
reg = <0x0202c000 0x4000>;
interrupts = <0 47 0x04>;
clocks = <&clks 179>;
fsl,fifo-depth = <15>;
fsl,ssi-dma-events = <42 41>;
status = "disabled";
};
ssi3: ssi@02030000 {
compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
reg = <0x02030000 0x4000>;
interrupts = <0 48 0x04>;
clocks = <&clks 180>;
fsl,fifo-depth = <15>;
fsl,ssi-dma-events = <46 45>;
status = "disabled";
};
asrc: asrc@02034000 {
reg = <0x02034000 0x4000>;
interrupts = <0 50 0x04>;
};
spba@0203c000 {
reg = <0x0203c000 0x4000>;
};
};
vpu: vpu@02040000 {
reg = <0x02040000 0x3c000>;
interrupts = <0 3 0x04 0 12 0x04>;
};
aipstz@0207c000 { /* AIPSTZ1 */
reg = <0x0207c000 0x4000>;
};
pwm1: pwm@02080000 {
#pwm-cells = <2>;
compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
reg = <0x02080000 0x4000>;
interrupts = <0 83 0x04>;
clocks = <&clks 62>, <&clks 145>;
clock-names = "ipg", "per";
};
pwm2: pwm@02084000 {
#pwm-cells = <2>;
compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
reg = <0x02084000 0x4000>;
interrupts = <0 84 0x04>;
clocks = <&clks 62>, <&clks 146>;
clock-names = "ipg", "per";
};
pwm3: pwm@02088000 {
#pwm-cells = <2>;
compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
reg = <0x02088000 0x4000>;
interrupts = <0 85 0x04>;
clocks = <&clks 62>, <&clks 147>;
clock-names = "ipg", "per";
};
pwm4: pwm@0208c000 {
#pwm-cells = <2>;
compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
reg = <0x0208c000 0x4000>;
interrupts = <0 86 0x04>;
clocks = <&clks 62>, <&clks 148>;
clock-names = "ipg", "per";
};
can1: flexcan@02090000 {
reg = <0x02090000 0x4000>;
interrupts = <0 110 0x04>;
};
can2: flexcan@02094000 {
reg = <0x02094000 0x4000>;
interrupts = <0 111 0x04>;
};
gpt: gpt@02098000 {
compatible = "fsl,imx6q-gpt";
reg = <0x02098000 0x4000>;
interrupts = <0 55 0x04>;
};
gpio1: gpio@0209c000 {
compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
reg = <0x0209c000 0x4000>;
interrupts = <0 66 0x04 0 67 0x04>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio2: gpio@020a0000 {
compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
reg = <0x020a0000 0x4000>;
interrupts = <0 68 0x04 0 69 0x04>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio3: gpio@020a4000 {
compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
reg = <0x020a4000 0x4000>;
interrupts = <0 70 0x04 0 71 0x04>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio4: gpio@020a8000 {
compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
reg = <0x020a8000 0x4000>;
interrupts = <0 72 0x04 0 73 0x04>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio5: gpio@020ac000 {
compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
reg = <0x020ac000 0x4000>;
interrupts = <0 74 0x04 0 75 0x04>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio6: gpio@020b0000 {
compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
reg = <0x020b0000 0x4000>;
interrupts = <0 76 0x04 0 77 0x04>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio7: gpio@020b4000 {
compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
reg = <0x020b4000 0x4000>;
interrupts = <0 78 0x04 0 79 0x04>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
kpp: kpp@020b8000 {
reg = <0x020b8000 0x4000>;
interrupts = <0 82 0x04>;
};
wdog1: wdog@020bc000 {
compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
reg = <0x020bc000 0x4000>;
interrupts = <0 80 0x04>;
clocks = <&clks 0>;
};
wdog2: wdog@020c0000 {
compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
reg = <0x020c0000 0x4000>;
interrupts = <0 81 0x04>;
clocks = <&clks 0>;
status = "disabled";
};
clks: ccm@020c4000 {
compatible = "fsl,imx6q-ccm";
reg = <0x020c4000 0x4000>;
interrupts = <0 87 0x04 0 88 0x04>;
#clock-cells = <1>;
};
anatop: anatop@020c8000 {
compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
reg = <0x020c8000 0x1000>;
interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>;
regulator-1p1@110 {
compatible = "fsl,anatop-regulator";
regulator-name = "vdd1p1";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1375000>;
regulator-always-on;
anatop-reg-offset = <0x110>;
anatop-vol-bit-shift = <8>;
anatop-vol-bit-width = <5>;
anatop-min-bit-val = <4>;
anatop-min-voltage = <800000>;
anatop-max-voltage = <1375000>;
};
regulator-3p0@120 {
compatible = "fsl,anatop-regulator";
regulator-name = "vdd3p0";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <3150000>;
regulator-always-on;
anatop-reg-offset = <0x120>;
anatop-vol-bit-shift = <8>;
anatop-vol-bit-width = <5>;
anatop-min-bit-val = <0>;
anatop-min-voltage = <2625000>;
anatop-max-voltage = <3400000>;
};
regulator-2p5@130 {
compatible = "fsl,anatop-regulator";
regulator-name = "vdd2p5";
regulator-min-microvolt = <2000000>;
regulator-max-microvolt = <2750000>;
regulator-always-on;
anatop-reg-offset = <0x130>;
anatop-vol-bit-shift = <8>;
anatop-vol-bit-width = <5>;
anatop-min-bit-val = <0>;
anatop-min-voltage = <2000000>;
anatop-max-voltage = <2750000>;
};
reg_arm: regulator-vddcore@140 {
compatible = "fsl,anatop-regulator";
regulator-name = "cpu";
regulator-min-microvolt = <725000>;
regulator-max-microvolt = <1450000>;
regulator-always-on;
anatop-reg-offset = <0x140>;
anatop-vol-bit-shift = <0>;
anatop-vol-bit-width = <5>;
anatop-delay-reg-offset = <0x170>;
anatop-delay-bit-shift = <24>;
anatop-delay-bit-width = <2>;
anatop-min-bit-val = <1>;
anatop-min-voltage = <725000>;
anatop-max-voltage = <1450000>;
};
reg_pu: regulator-vddpu@140 {
compatible = "fsl,anatop-regulator";
regulator-name = "vddpu";
regulator-min-microvolt = <725000>;
regulator-max-microvolt = <1450000>;
regulator-always-on;
anatop-reg-offset = <0x140>;
anatop-vol-bit-shift = <9>;
anatop-vol-bit-width = <5>;
anatop-delay-reg-offset = <0x170>;
anatop-delay-bit-shift = <26>;
anatop-delay-bit-width = <2>;
anatop-min-bit-val = <1>;
anatop-min-voltage = <725000>;
anatop-max-voltage = <1450000>;
};
reg_soc: regulator-vddsoc@140 {
compatible = "fsl,anatop-regulator";
regulator-name = "vddsoc";
regulator-min-microvolt = <725000>;
regulator-max-microvolt = <1450000>;
regulator-always-on;
anatop-reg-offset = <0x140>;
anatop-vol-bit-shift = <18>;
anatop-vol-bit-width = <5>;
anatop-delay-reg-offset = <0x170>;
anatop-delay-bit-shift = <28>;
anatop-delay-bit-width = <2>;
anatop-min-bit-val = <1>;
anatop-min-voltage = <725000>;
anatop-max-voltage = <1450000>;
};
};
usbphy1: usbphy@020c9000 {
compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
reg = <0x020c9000 0x1000>;
interrupts = <0 44 0x04>;
clocks = <&clks 182>;
};
usbphy2: usbphy@020ca000 {
compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
reg = <0x020ca000 0x1000>;
interrupts = <0 45 0x04>;
clocks = <&clks 183>;
};
snvs@020cc000 {
compatible = "fsl,sec-v4.0-mon", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x020cc000 0x4000>;
snvs-rtc-lp@34 {
compatible = "fsl,sec-v4.0-mon-rtc-lp";
reg = <0x34 0x58>;
interrupts = <0 19 0x04 0 20 0x04>;
};
};
epit1: epit@020d0000 { /* EPIT1 */
reg = <0x020d0000 0x4000>;
interrupts = <0 56 0x04>;
};
epit2: epit@020d4000 { /* EPIT2 */
reg = <0x020d4000 0x4000>;
interrupts = <0 57 0x04>;
};
src: src@020d8000 {
compatible = "fsl,imx6q-src";
reg = <0x020d8000 0x4000>;
interrupts = <0 91 0x04 0 96 0x04>;
};
gpc: gpc@020dc000 {
compatible = "fsl,imx6q-gpc";
reg = <0x020dc000 0x4000>;
interrupts = <0 89 0x04 0 90 0x04>;
};
gpr: iomuxc-gpr@020e0000 {
compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
reg = <0x020e0000 0x38>;
};
dcic1: dcic@020e4000 {
reg = <0x020e4000 0x4000>;
interrupts = <0 124 0x04>;
};
dcic2: dcic@020e8000 {
reg = <0x020e8000 0x4000>;
interrupts = <0 125 0x04>;
};
sdma: sdma@020ec000 {
compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
reg = <0x020ec000 0x4000>;
interrupts = <0 2 0x04>;
clocks = <&clks 155>, <&clks 155>;
clock-names = "ipg", "ahb";
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
};
};
aips-bus@02100000 { /* AIPS2 */
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x02100000 0x100000>;
ranges;
caam@02100000 {
reg = <0x02100000 0x40000>;
interrupts = <0 105 0x04 0 106 0x04>;
};
aipstz@0217c000 { /* AIPSTZ2 */
reg = <0x0217c000 0x4000>;
};
usbotg: usb@02184000 {
compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
reg = <0x02184000 0x200>;
interrupts = <0 43 0x04>;
clocks = <&clks 162>;
fsl,usbphy = <&usbphy1>;
fsl,usbmisc = <&usbmisc 0>;
status = "disabled";
};
usbh1: usb@02184200 {
compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
reg = <0x02184200 0x200>;
interrupts = <0 40 0x04>;
clocks = <&clks 162>;
fsl,usbphy = <&usbphy2>;
fsl,usbmisc = <&usbmisc 1>;
status = "disabled";
};
usbh2: usb@02184400 {
compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
reg = <0x02184400 0x200>;
interrupts = <0 41 0x04>;
clocks = <&clks 162>;
fsl,usbmisc = <&usbmisc 2>;
status = "disabled";
};
usbh3: usb@02184600 {
compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
reg = <0x02184600 0x200>;
interrupts = <0 42 0x04>;
clocks = <&clks 162>;
fsl,usbmisc = <&usbmisc 3>;
status = "disabled";
};
usbmisc: usbmisc: usbmisc@02184800 {
#index-cells = <1>;
compatible = "fsl,imx6q-usbmisc";
reg = <0x02184800 0x200>;
clocks = <&clks 162>;
};
fec: ethernet@02188000 {
compatible = "fsl,imx6q-fec";
reg = <0x02188000 0x4000>;
interrupts = <0 118 0x04 0 119 0x04>;
clocks = <&clks 117>, <&clks 117>, <&clks 190>;
clock-names = "ipg", "ahb", "ptp";
status = "disabled";
};
mlb@0218c000 {
reg = <0x0218c000 0x4000>;
interrupts = <0 53 0x04 0 117 0x04 0 126 0x04>;
};
usdhc1: usdhc@02190000 {
compatible = "fsl,imx6q-usdhc";
reg = <0x02190000 0x4000>;
interrupts = <0 22 0x04>;
clocks = <&clks 163>, <&clks 163>, <&clks 163>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
status = "disabled";
};
usdhc2: usdhc@02194000 {
compatible = "fsl,imx6q-usdhc";
reg = <0x02194000 0x4000>;
interrupts = <0 23 0x04>;
clocks = <&clks 164>, <&clks 164>, <&clks 164>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
status = "disabled";
};
usdhc3: usdhc@02198000 {
compatible = "fsl,imx6q-usdhc";
reg = <0x02198000 0x4000>;
interrupts = <0 24 0x04>;
clocks = <&clks 165>, <&clks 165>, <&clks 165>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
status = "disabled";
};
usdhc4: usdhc@0219c000 {
compatible = "fsl,imx6q-usdhc";
reg = <0x0219c000 0x4000>;
interrupts = <0 25 0x04>;
clocks = <&clks 166>, <&clks 166>, <&clks 166>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
status = "disabled";
};
i2c1: i2c@021a0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
reg = <0x021a0000 0x4000>;
interrupts = <0 36 0x04>;
clocks = <&clks 125>;
status = "disabled";
};
i2c2: i2c@021a4000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
reg = <0x021a4000 0x4000>;
interrupts = <0 37 0x04>;
clocks = <&clks 126>;
status = "disabled";
};
i2c3: i2c@021a8000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
reg = <0x021a8000 0x4000>;
interrupts = <0 38 0x04>;
clocks = <&clks 127>;
status = "disabled";
};
romcp@021ac000 {
reg = <0x021ac000 0x4000>;
};
mmdc0: mmdc@021b0000 { /* MMDC0 */
compatible = "fsl,imx6q-mmdc";
reg = <0x021b0000 0x4000>;
};
mmdc1: mmdc@021b4000 { /* MMDC1 */
reg = <0x021b4000 0x4000>;
};
weim@021b8000 {
reg = <0x021b8000 0x4000>;
interrupts = <0 14 0x04>;
};
ocotp@021bc000 {
compatible = "fsl,imx6q-ocotp";
reg = <0x021bc000 0x4000>;
};
ocotp@021c0000 {
reg = <0x021c0000 0x4000>;
interrupts = <0 21 0x04>;
};
tzasc@021d0000 { /* TZASC1 */
reg = <0x021d0000 0x4000>;
interrupts = <0 108 0x04>;
};
tzasc@021d4000 { /* TZASC2 */
reg = <0x021d4000 0x4000>;
interrupts = <0 109 0x04>;
};
audmux: audmux@021d8000 {
compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
reg = <0x021d8000 0x4000>;
status = "disabled";
};
mipi@021dc000 { /* MIPI-CSI */
reg = <0x021dc000 0x4000>;
};
mipi@021e0000 { /* MIPI-DSI */
reg = <0x021e0000 0x4000>;
};
vdoa@021e4000 {
reg = <0x021e4000 0x4000>;
interrupts = <0 18 0x04>;
};
uart2: serial@021e8000 {
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
reg = <0x021e8000 0x4000>;
interrupts = <0 27 0x04>;
clocks = <&clks 160>, <&clks 161>;
clock-names = "ipg", "per";
status = "disabled";
};
uart3: serial@021ec000 {
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
reg = <0x021ec000 0x4000>;
interrupts = <0 28 0x04>;
clocks = <&clks 160>, <&clks 161>;
clock-names = "ipg", "per";
status = "disabled";
};
uart4: serial@021f0000 {
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
reg = <0x021f0000 0x4000>;
interrupts = <0 29 0x04>;
clocks = <&clks 160>, <&clks 161>;
clock-names = "ipg", "per";
status = "disabled";
};
uart5: serial@021f4000 {
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
reg = <0x021f4000 0x4000>;
interrupts = <0 30 0x04>;
clocks = <&clks 160>, <&clks 161>;
clock-names = "ipg", "per";
status = "disabled";
};
};
ipu1: ipu@02400000 {
#crtc-cells = <1>;
compatible = "fsl,imx6q-ipu";
reg = <0x02400000 0x400000>;
interrupts = <0 6 0x4 0 5 0x4>;
clocks = <&clks 130>, <&clks 131>, <&clks 132>;
clock-names = "bus", "di0", "di1";
};
};
};

4
arch/arm/mach-imx/clk-imx51-imx53.c
View file

@ -83,6 +83,7 @@ enum imx5_clks {
ssi2_root_gate, ssi3_root_gate, ssi_ext1_gate, ssi_ext2_gate,
epit1_ipg_gate, epit1_hf_gate, epit2_ipg_gate, epit2_hf_gate,
can_sel, can1_serial_gate, can1_ipg_gate,
owire_gate,
clk_max
};
@ -233,12 +234,13 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
clk[epit1_hf_gate] = imx_clk_gate2("epit1_hf_gate", "per_root", MXC_CCM_CCGR2, 4);
clk[epit2_ipg_gate] = imx_clk_gate2("epit2_ipg_gate", "ipg", MXC_CCM_CCGR2, 6);
clk[epit2_hf_gate] = imx_clk_gate2("epit2_hf_gate", "per_root", MXC_CCM_CCGR2, 8);
clk[owire_gate] = imx_clk_gate2("owire_gate", "per_root", MXC_CCM_CCGR2, 22);
for (i = 0; i < ARRAY_SIZE(clk); i++)
if (IS_ERR(clk[i]))
pr_err("i.MX5 clk %d: register failed with %ld\n",
i, PTR_ERR(clk[i]));
clk_register_clkdev(clk[gpt_hf_gate], "per", "imx-gpt.0");
clk_register_clkdev(clk[gpt_ipg_gate], "ipg", "imx-gpt.0");
clk_register_clkdev(clk[uart1_per_gate], "per", "imx21-uart.0");

26
arch/arm/mach-imx/clk-imx6q.c
View file

@ -154,8 +154,8 @@ enum mx6q_clks {
usdhc4, vdo_axi, vpu_axi, cko1, pll1_sys, pll2_bus, pll3_usb_otg,
pll4_audio, pll5_video, pll8_mlb, pll7_usb_host, pll6_enet, ssi1_ipg,
ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2, ldb_di0_div_3_5, ldb_di1_div_3_5,
sata_ref, sata_ref_100m, pcie_ref, pcie_ref_125m, enet_ref,
clk_max
sata_ref, sata_ref_100m, pcie_ref, pcie_ref_125m, enet_ref, usbphy1_gate,
usbphy2_gate, clk_max
};
static struct clk *clk[clk_max];
@ -208,8 +208,21 @@ int __init mx6q_clocks_init(void)
clk[pll7_usb_host] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7_usb_host","osc", base + 0x20, 0x3);
clk[pll8_mlb] = imx_clk_pllv3(IMX_PLLV3_MLB, "pll8_mlb", "osc", base + 0xd0, 0x0);
clk[usbphy1] = imx_clk_gate("usbphy1", "pll3_usb_otg", base + 0x10, 6);
clk[usbphy2] = imx_clk_gate("usbphy2", "pll7_usb_host", base + 0x20, 6);
/*
* Bit 20 is the reserved and read-only bit, we do this only for:
* - Do nothing for usbphy clk_enable/disable
* - Keep refcount when do usbphy clk_enable/disable, in that case,
* the clk framework may need to enable/disable usbphy's parent
*/
clk[usbphy1] = imx_clk_gate("usbphy1", "pll3_usb_otg", base + 0x10, 20);
clk[usbphy2] = imx_clk_gate("usbphy2", "pll7_usb_host", base + 0x20, 20);
/*
* usbphy*_gate needs to be on after system boots up, and software
* never needs to control it anymore.
*/
clk[usbphy1_gate] = imx_clk_gate("usbphy1_gate", "dummy", base + 0x10, 6);
clk[usbphy2_gate] = imx_clk_gate("usbphy2_gate", "dummy", base + 0x20, 6);
clk[sata_ref] = imx_clk_fixed_factor("sata_ref", "pll6_enet", 1, 5);
clk[pcie_ref] = imx_clk_fixed_factor("pcie_ref", "pll6_enet", 1, 4);
@ -436,6 +449,11 @@ int __init mx6q_clocks_init(void)
for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
clk_prepare_enable(clk[clks_init_on[i]]);
if (IS_ENABLED(CONFIG_USB_MXS_PHY)) {
clk_prepare_enable(clk[usbphy1_gate]);
clk_prepare_enable(clk[usbphy2_gate]);
}
/* Set initial power mode */
imx6q_set_lpm(WAIT_CLOCKED);

65
arch/arm/mach-imx/mach-imx6q.c
View file

@ -12,6 +12,7 @@
#include <linux/clk.h>
#include <linux/clkdev.h>
#include <linux/cpu.h>
#include <linux/cpuidle.h>
#include <linux/delay.h>
#include <linux/export.h>
@ -22,6 +23,7 @@
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/opp.h>
#include <linux/phy.h>
#include <linux/regmap.h>
#include <linux/micrel_phy.h>
@ -209,9 +211,72 @@ static struct cpuidle_driver imx6q_cpuidle_driver = {
.state_count = 1,
};
#define OCOTP_CFG3 0x440
#define OCOTP_CFG3_SPEED_SHIFT 16
#define OCOTP_CFG3_SPEED_1P2GHZ 0x3
static void __init imx6q_opp_check_1p2ghz(struct device *cpu_dev)
{
struct device_node *np;
void __iomem *base;
u32 val;
np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-ocotp");
if (!np) {
pr_warn("failed to find ocotp node\n");
return;
}
base = of_iomap(np, 0);
if (!base) {
pr_warn("failed to map ocotp\n");
goto put_node;
}
val = readl_relaxed(base + OCOTP_CFG3);
val >>= OCOTP_CFG3_SPEED_SHIFT;
if ((val & 0x3) != OCOTP_CFG3_SPEED_1P2GHZ)
if (opp_disable(cpu_dev, 1200000000))
pr_warn("failed to disable 1.2 GHz OPP\n");
put_node:
of_node_put(np);
}
static void __init imx6q_opp_init(struct device *cpu_dev)
{
struct device_node *np;
np = of_find_node_by_path("/cpus/cpu@0");
if (!np) {
pr_warn("failed to find cpu0 node\n");
return;
}
cpu_dev->of_node = np;
if (of_init_opp_table(cpu_dev)) {
pr_warn("failed to init OPP table\n");
goto put_node;
}
imx6q_opp_check_1p2ghz(cpu_dev);
put_node:
of_node_put(np);
}
struct platform_device imx6q_cpufreq_pdev = {
.name = "imx6q-cpufreq",
};
static void __init imx6q_init_late(void)
{
imx_cpuidle_init(&imx6q_cpuidle_driver);
if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ)) {
imx6q_opp_init(&imx6q_cpufreq_pdev.dev);
platform_device_register(&imx6q_cpufreq_pdev);
}
}
static void __init imx6q_map_io(void)

9
drivers/w1/masters/mxc_w1.c
View file

@ -186,9 +186,16 @@ static int mxc_w1_remove(struct platform_device *pdev)
return 0;
}
static struct of_device_id mxc_w1_dt_ids[] = {
{ .compatible = "fsl,imx21-owire" },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, mxc_w1_dt_ids);
static struct platform_driver mxc_w1_driver = {
.driver = {
.name = "mxc_w1",
.name = "mxc_w1",
.of_match_table = mxc_w1_dt_ids,
},
.probe = mxc_w1_probe,
.remove = mxc_w1_remove,