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Qualcomm ARM DTS updates for 6.1

Browse source 
This adds extends the IPQ8064 support with the two variants IPQ8062 and
 IPQ8065. MSM8974 and APQ8084 gained RPM stats support.
 
 The Audio DSP remoteproc was added to MSM8226 and enabled for ASUS
 ZenWatch 2 and LG G Watch R.
 
 MSM8660 gained one I2C and one SPI bus and the APQ8060 Dragonboard got
 the TMA340 Touchscreen described.
 
 A wide range of improvements are done throughout the DTS files to align
 with bindings, fix issues and improve structure on things.
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Merge tag 'qcom-dts-for-6.1' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/dt

Qualcomm ARM DTS updates for 6.1

This adds extends the IPQ8064 support with the two variants IPQ8062 and
IPQ8065. MSM8974 and APQ8084 gained RPM stats support.

The Audio DSP remoteproc was added to MSM8226 and enabled for ASUS
ZenWatch 2 and LG G Watch R.

MSM8660 gained one I2C and one SPI bus and the APQ8060 Dragonboard got
the TMA340 Touchscreen described.

A wide range of improvements are done throughout the DTS files to align
with bindings, fix issues and improve structure on things.

* tag 'qcom-dts-for-6.1' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (35 commits)
  ARM: dts: qcom: apq8026-lg-lenok: Enable ADSP
  ARM: dts: qcom: apq8026-asus-sparrow: Enable ADSP
  ARM: dts: qcom: msm8226: Add ADSP node
  ARM: dts: qcom: ipq8064: pad addresses to 8 digit
  ARM: dts: qcom: ipq8064: reorganize node order and sort them
  ARM: dts: qcom: align SDHCI clocks with DT schema
  ARM: dts: qcom: align SDHCI reg-names with DT schema
  ARM: dts: qcom: msm8960: add clocks to the MMCC device node
  ARM: dts: qcom: apq8064: add clocks to the MMCC device node
  ARM: dts: qcom: msm8960: add clocks to the GCC device node
  ARM: dts: qcom: apq8064: add clocks to the GCC device node
  ARM: dts: qcom: msm8960: add clocks to the LCC device node
  ARM: dts: qcom: apq8064: add clocks to the LCC device node
  ARM: dts: qcom: msm8226: switch TCSR mutex to MMIO
  ARM: dts: qcom: apq8084: switch TCSR mutex to MMIO
  ARM: dts: qcom: msm8660: fix node names for fixed clocks
  ARM: dts: qcom: msm8660: add pxo/cxo clocks to the GCC node
  ARM: dts: qcom: apq8060-dragonboard: Add TMA340 to APQ8060 DragonBoard
  ARM: dts: qcom: msm8660: Add GSBI3 I2C bus
  ARM: dts: qcom: msm8660: Add GSBI1 SPI bus
  ...

Link: https://lore.kernel.org/r/20220921222619.1338380-1-andersson@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2022-09-23 16:35:16 +02:00
commit 78559d6fb8
32 changed files with 1286 additions and 815 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

6
arch/arm/boot/dts/qcom-apq8026-asus-sparrow.dts
View file

@ -8,6 +8,8 @@
#include "qcom-msm8226.dtsi"
#include "qcom-pm8226.dtsi"
/delete-node/ &adsp_region;
/ {
model = "ASUS ZenWatch 2";
compatible = "asus,sparrow", "qcom,apq8026";
@ -57,6 +59,10 @@ vreg_wlan: wlan-regulator {
};
};
&adsp {
status = "okay";
};
&blsp1_uart1 {
status = "okay";

13
arch/arm/boot/dts/qcom-apq8026-lg-lenok.dts
View file

@ -8,6 +8,8 @@
#include "qcom-msm8226.dtsi"
#include "qcom-pm8226.dtsi"
/delete-node/ &adsp_region;
/ {
model = "LG G Watch R";
compatible = "lg,lenok", "qcom,apq8026";
@ -23,6 +25,13 @@ chosen {
stdout-path = "serial0:115200n8";
};
reserved-memory {
adsp_region: adsp@3300000 {
reg = <0x03300000 0x1400000>;
no-map;
};
};
vreg_wlan: wlan-regulator {
compatible = "regulator-fixed";
@ -38,6 +47,10 @@ vreg_wlan: wlan-regulator {
};
};
&adsp {
status = "okay";
};
&blsp1_i2c1 {
status = "okay";

71
arch/arm/boot/dts/qcom-apq8060-dragonboard.dts
View file

@ -159,6 +159,19 @@ data {
};
};
dragon_gsbi3_i2c_pins: gsbi3_i2c {
mux {
pins = "gpio43", "gpio44";
function = "gsbi3";
};
pinconf {
pins = "gpio43", "gpio44";
drive-strength = <8>;
/* These have external pull-up 2.2kOhm to 1.8V */
bias-disable;
};
};
dragon_gsbi8_i2c_pins: gsbi8_i2c {
mux {
pins = "gpio64", "gpio65";
@ -240,6 +253,22 @@ irq {
bias-pull-up;
};
};
dragon_tma340_gpios: tma340 {
reset {
/* RESET line, TS_ATTN, WAKE_CTP */
pins = "gpio58";
function = "gpio";
drive-strength = <6>;
bias-disable;
};
irq {
pins = "gpio61"; /* IRQ line */
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
};
};
qcom,ssbi@500000 {
@ -444,6 +473,45 @@ led@133 {
};
};
gsbi@16200000 {
qcom,mode = <GSBI_PROT_I2C>;
status = "okay";
gsbi3_i2c: i2c@16280000 {
pinctrl-names = "default";
pinctrl-0 = <&dragon_gsbi3_i2c_pins>;
status = "okay";
touchscreen@24 {
compatible = "cypress,cy8ctma340";
reg = <0x24>;
/* Certainly we can do at least 400 kHz */
clock-frequency = <400000>;
/* IRQ on GPIO61 called /CTP_INT */
interrupt-parent = <&tlmm>;
interrupts = <61 IRQ_TYPE_EDGE_FALLING>;
/*
* The I2C bus is using a PCA9306 level translator from L16A
* to L2B so these two voltages are needed and L16A is
* kind of the IO voltage, however L16Aisn't really fed to
* the TMA340, which relies entirely on L2B (PM8901 L2).
*/
vcpin-supply = <&pm8058_l16>;
vdd-supply = <&pm8901_l2>;
/* GPIO58, called WAKE_CTP */
reset-gpios = <&tlmm 58 GPIO_ACTIVE_LOW>;
touchscreen-size-x = <480>;
touchscreen-size-y = <800>;
active-interval-ms = <0>;
touch-timeout-ms = <255>;
lowpower-interval-ms = <10>;
bootloader-key = /bits/ 8 <0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07>;
pinctrl-names = "default";
pinctrl-0 = <&dragon_tma340_gpios>;
};
};
};
gsbi@19800000 {
status = "okay";
qcom,mode = <GSBI_PROT_I2C>;
@ -634,7 +702,8 @@ l1 {
bias-pull-down;
};
l2 {
regulator-min-microvolt = <2850000>;
/* TMA340 requires strictly 3.3V */
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
bias-pull-down;
};

2
arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts
View file

@ -215,7 +215,7 @@ pci@1b500000 {
vdda_refclk-supply = <&v3p3_fixed>;
pinctrl-0 = <&pcie_pins>;
pinctrl-names = "default";
perst-gpio = <&tlmm_pinmux 27 GPIO_ACTIVE_LOW>;
perst-gpios = <&tlmm_pinmux 27 GPIO_ACTIVE_LOW>;
};
amba {

2
arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
View file

@ -287,7 +287,7 @@ pci@1b500000 {
vdda_refclk-supply = <&ext_3p3v>;
pinctrl-0 = <&pcie_pins>;
pinctrl-names = "default";
perst-gpio = <&tlmm_pinmux 27 GPIO_ACTIVE_LOW>;
perst-gpios = <&tlmm_pinmux 27 GPIO_ACTIVE_LOW>;
};
qcom,ssbi@500000 {

37
arch/arm/boot/dts/qcom-apq8064.dtsi
View file

@ -2,6 +2,7 @@
/dts-v1/;
#include <dt-bindings/clock/qcom,gcc-msm8960.h>
#include <dt-bindings/clock/qcom,lcc-msm8960.h>
#include <dt-bindings/reset/qcom,gcc-msm8960.h>
#include <dt-bindings/clock/qcom,mmcc-msm8960.h>
#include <dt-bindings/clock/qcom,rpmcc.h>
@ -815,6 +816,10 @@ gcc: clock-controller@900000 {
#clock-cells = <1>;
#power-domain-cells = <1>;
#reset-cells = <1>;
clocks = <&cxo_board>,
<&pxo_board>,
<&lcc PLL4>;
clock-names = "cxo", "pxo", "pll4";
tsens: thermal-sensor {
compatible = "qcom,msm8960-tsens";
@ -834,6 +839,20 @@ lcc: clock-controller@28000000 {
reg = <0x28000000 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
clocks = <&pxo_board>,
<&gcc PLL4_VOTE>,
<0>,
<0>, <0>,
<0>, <0>,
<0>;
clock-names = "pxo",
"pll4_vote",
"mi2s_codec_clk",
"codec_i2s_mic_codec_clk",
"spare_i2s_mic_codec_clk",
"codec_i2s_spkr_codec_clk",
"spare_i2s_spkr_codec_clk",
"pcm_codec_clk";
};
mmcc: clock-controller@4000000 {
@ -842,6 +861,22 @@ mmcc: clock-controller@4000000 {
#clock-cells = <1>;
#power-domain-cells = <1>;
#reset-cells = <1>;
clocks = <&pxo_board>,
<&gcc PLL3>,
<&gcc PLL8_VOTE>,
<&dsi0_phy 1>,
<&dsi0_phy 0>,
<0>,
<0>,
<0>;
clock-names = "pxo",
"pll3",
"pll8_vote",
"dsi1pll",
"dsi1pllbyte",
"dsi2pll",
"dsi2pllbyte",
"hdmipll";
};
l2cc: clock-controller@2011000 {
@ -1384,7 +1419,7 @@ gfx3d1: iommu@7d00000 {
};
pcie: pci@1b500000 {
compatible = "qcom,pcie-apq8064", "snps,dw-pcie";
compatible = "qcom,pcie-apq8064";
reg = <0x1b500000 0x1000>,
<0x1b502000 0x80>,
<0x1b600000 0x100>,

3
arch/arm/boot/dts/qcom-apq8074-dragonboard.dts
View file

@ -1,4 +1,5 @@
// SPDX-License-Identifier: GPL-2.0
#include <dt-bindings/gpio/gpio.h>
#include "qcom-msm8974.dtsi"
#include "qcom-pm8841.dtsi"
#include "qcom-pm8941.dtsi"
@ -261,7 +262,7 @@ &sdhc_1 {
&sdhc_2 {
status = "okay";
cd-gpios = <&tlmm 62 0x1>;
cd-gpios = <&tlmm 62 GPIO_ACTIVE_LOW>;
vmmc-supply = <&pm8941_l21>;
vqmmc-supply = <&pm8941_l13>;

32
arch/arm/boot/dts/qcom-apq8084.dtsi
View file

@ -239,6 +239,11 @@ apcs: syscon@f9011000 {
reg = <0xf9011000 0x1000>;
};
sram@fc190000 {
compatible = "qcom,apq8084-rpm-stats";
reg = <0xfc190000 0x10000>;
};
qfprom: qfprom@fc4bc000 {
compatible = "qcom,apq8084-qfprom", "qcom,qfprom";
reg = <0xfc4bc000 0x1000>;
@ -383,14 +388,9 @@ gcc: clock-controller@fc400000 {
reg = <0xfc400000 0x4000>;
};
tcsr_mutex_regs: syscon@fd484000 {
compatible = "syscon";
reg = <0xfd484000 0x2000>;
};
tcsr_mutex: hwlock {
compatible = "qcom,tcsr-mutex";
syscon = <&tcsr_mutex_regs 0 0x80>;
tcsr_mutex: hwlock@fd484000 {
compatible = "qcom,apq8084-tcsr-mutex", "qcom,tcsr-mutex";
reg = <0xfd484000 0x1000>;
#hwlock-cells = <1>;
};
@ -422,26 +422,26 @@ blsp2_uart2: serial@f995e000 {
mmc@f9824900 {
compatible = "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4";
reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
reg-names = "hc_mem", "core_mem";
reg-names = "hc", "core";
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
clocks = <&gcc GCC_SDCC1_APPS_CLK>,
<&gcc GCC_SDCC1_AHB_CLK>,
clocks = <&gcc GCC_SDCC1_AHB_CLK>,
<&gcc GCC_SDCC1_APPS_CLK>,
<&xo_board>;
clock-names = "core", "iface", "xo";
clock-names = "iface", "core", "xo";
status = "disabled";
};
mmc@f98a4900 {
compatible = "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4";
reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
reg-names = "hc_mem", "core_mem";
reg-names = "hc", "core";
interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
clocks = <&gcc GCC_SDCC2_APPS_CLK>,
<&gcc GCC_SDCC2_AHB_CLK>,
clocks = <&gcc GCC_SDCC2_AHB_CLK>,
<&gcc GCC_SDCC2_APPS_CLK>,
<&xo_board>;
clock-names = "core", "iface", "xo";
clock-names = "iface", "core", "xo";
status = "disabled";
};

3
arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
View file

@ -14,6 +14,7 @@
*
*/
#include <dt-bindings/gpio/gpio.h>
#include "qcom-ipq4019.dtsi"
/ {
@ -72,7 +73,7 @@ spi@78b5000 {
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
status = "okay";
cs-gpios = <&tlmm 54 0>;
cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
mx25l25635e@0 {
#address-cells = <1>;

4
arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
View file

@ -87,7 +87,7 @@ spi@78b5000 { /* BLSP1 QUP1 */
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
status = "okay";
cs-gpios = <&tlmm 12 0>;
cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
flash@0 {
#address-cells = <1>;
@ -100,7 +100,7 @@ flash@0 {
pci@40000000 {
status = "okay";
perst-gpio = <&tlmm 38 0x1>;
perst-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>;
};
qpic-nand@79b0000 {

5
arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts
View file

@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2018, The Linux Foundation. All rights reserved.
#include <dt-bindings/gpio/gpio.h>
#include "qcom-ipq4019-ap.dk07.1.dtsi"
/ {
@ -10,7 +11,7 @@ / {
soc {
pci@40000000 {
status = "okay";
perst-gpio = <&tlmm 38 0x1>;
perst-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>;
};
spi@78b6000 {
@ -50,7 +51,7 @@ spi@78b5000 {
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
status = "okay";
cs-gpios = <&tlmm 12 0>;
cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
flash@0 {
#address-cells = <1>;

7
arch/arm/boot/dts/qcom-ipq4019.dtsi
View file

@ -224,12 +224,13 @@ vqmmc: regulator@1948000 {
sdhci: mmc@7824900 {
compatible = "qcom,sdhci-msm-v4";
reg = <0x7824900 0x11c>, <0x7824000 0x800>;
reg-names = "hc", "core";
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
bus-width = <8>;
clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>,
clocks = <&gcc GCC_SDCC1_AHB_CLK>, <&gcc GCC_SDCC1_APPS_CLK>,
<&gcc GCC_DCD_XO_CLK>;
clock-names = "core", "iface", "xo";
clock-names = "iface", "core", "xo";
status = "disabled";
};
@ -412,7 +413,7 @@ restart@4ab000 {
};
pcie0: pci@40000000 {
compatible = "qcom,pcie-ipq4019", "snps,dw-pcie";
compatible = "qcom,pcie-ipq4019";
reg = <0x40000000 0xf1d
0x40000f20 0xa8
0x80000 0x2000

37
arch/arm/boot/dts/qcom-ipq8062-smb208.dtsi Normal file
View file

@ -0,0 +1,37 @@
// SPDX-License-Identifier: GPL-2.0-only
#include "qcom-ipq8062.dtsi"
&rpm {
smb208_regulators: regulators {
compatible = "qcom,rpm-smb208-regulators";
smb208_s1a: s1a {
regulator-min-microvolt = <1050000>;
regulator-max-microvolt = <1150000>;
qcom,switch-mode-frequency = <1200000>;
};
smb208_s1b: s1b {
regulator-min-microvolt = <1050000>;
regulator-max-microvolt = <1150000>;
qcom,switch-mode-frequency = <1200000>;
};
smb208_s2a: s2a {
regulator-min-microvolt = < 800000>;
regulator-max-microvolt = <1150000>;
qcom,switch-mode-frequency = <1200000>;
};
smb208_s2b: s2b {
regulator-min-microvolt = < 800000>;
regulator-max-microvolt = <1150000>;
qcom,switch-mode-frequency = <1200000>;
};
};
};

8
arch/arm/boot/dts/qcom-ipq8062.dtsi Normal file
View file

@ -0,0 +1,8 @@
// SPDX-License-Identifier: GPL-2.0-only
#include "qcom-ipq8064-v2.0.dtsi"
/ {
model = "Qualcomm Technologies, Inc. IPQ8062";
compatible = "qcom,ipq8062", "qcom,ipq8064";
};

37
arch/arm/boot/dts/qcom-ipq8064-v2.0-smb208.dtsi Normal file
View file

@ -0,0 +1,37 @@
// SPDX-License-Identifier: GPL-2.0
#include "qcom-ipq8064-v2.0.dtsi"
&rpm {
smb208_regulators: regulators {
compatible = "qcom,rpm-smb208-regulators";
smb208_s1a: s1a {
regulator-min-microvolt = <1050000>;
regulator-max-microvolt = <1150000>;
qcom,switch-mode-frequency = <1200000>;
};
smb208_s1b: s1b {
regulator-min-microvolt = <1050000>;
regulator-max-microvolt = <1150000>;
qcom,switch-mode-frequency = <1200000>;
};
smb208_s2a: s2a {
regulator-min-microvolt = < 800000>;
regulator-max-microvolt = <1250000>;
qcom,switch-mode-frequency = <1200000>;
};
smb208_s2b: s2b {
regulator-min-microvolt = < 800000>;
regulator-max-microvolt = <1250000>;
qcom,switch-mode-frequency = <1200000>;
};
};
};

69
arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi Normal file
View file

@ -0,0 +1,69 @@
// SPDX-License-Identifier: GPL-2.0
#include "qcom-ipq8064.dtsi"
/ {
model = "Qualcomm Technologies, Inc. IPQ8064-v2.0";
aliases {
serial0 = &gsbi4_serial;
};
chosen {
stdout-path = "serial0:115200n8";
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
rsvd@41200000 {
reg = <0x41200000 0x300000>;
no-map;
};
};
};
&gsbi4 {
qcom,mode = <GSBI_PROT_I2C_UART>;
status = "okay";
serial@16340000 {
status = "okay";
};
/*
* The i2c device on gsbi4 should not be enabled.
* On ipq806x designs gsbi4 i2c is meant for exclusive
* RPM usage. Turning this on in kernel manifests as
* i2c failure for the RPM.
*/
};
&pcie0 {
compatible = "qcom,pcie-ipq8064-v2";
};
&pcie1 {
compatible = "qcom,pcie-ipq8064-v2";
};
&pcie2 {
compatible = "qcom,pcie-ipq8064-v2";
};
&sata {
ports-implemented = <0x1>;
};
&ss_phy_0 {
qcom,rx-eq = <2>;
qcom,tx-deamp_3_5db = <32>;
qcom,mpll = <5>;
};
&ss_phy_1 {
qcom,rx-eq = <2>;
qcom,tx-deamp_3_5db = <32>;
qcom,mpll = <5>;
};

775
arch/arm/boot/dts/qcom-ipq8064.dtsi
View file

@ -332,24 +332,64 @@ soc: soc {
ranges;
compatible = "simple-bus";
lpass@28100000 {
compatible = "qcom,lpass-cpu";
status = "disabled";
clocks = <&lcc AHBIX_CLK>,
<&lcc MI2S_OSR_CLK>,
<&lcc MI2S_BIT_CLK>;
clock-names = "ahbix-clk",
"mi2s-osr-clk",
"mi2s-bit-clk";
interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "lpass-irq-lpaif";
reg = <0x28100000 0x10000>;
reg-names = "lpass-lpaif";
stmmac_axi_setup: stmmac-axi-config {
snps,wr_osr_lmt = <7>;
snps,rd_osr_lmt = <7>;
snps,blen = <16 0 0 0 0 0 0>;
};
vsdcc_fixed: vsdcc-regulator {
compatible = "regulator-fixed";
regulator-name = "SDCC Power";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
rpm: rpm@108000 {
compatible = "qcom,rpm-ipq8064";
reg = <0x00108000 0x1000>;
qcom,ipc = <&l2cc 0x8 2>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ack", "err", "wakeup";
clocks = <&gcc RPM_MSG_RAM_H_CLK>;
clock-names = "ram";
rpmcc: clock-controller {
compatible = "qcom,rpmcc-ipq806x", "qcom,rpmcc";
#clock-cells = <1>;
};
};
qcom,ssbi@500000 {
compatible = "qcom,ssbi";
reg = <0x00500000 0x1000>;
qcom,controller-type = "pmic-arbiter";
};
qfprom: qfprom@700000 {
compatible = "qcom,ipq8064-qfprom", "qcom,qfprom";
reg = <0x00700000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
speedbin_efuse: speedbin@c0 {
reg = <0xc0 0x4>;
};
tsens_calib: calib@400 {
reg = <0x400 0xb>;
};
tsens_calib_backup: calib_backup@410 {
reg = <0x410 0xb>;
};
};
qcom_pinmux: pinmux@800000 {
compatible = "qcom,ipq8064-pinctrl";
reg = <0x800000 0x4000>;
reg = <0x00800000 0x4000>;
gpio-controller;
gpio-ranges = <&qcom_pinmux 0 0 69>;
@ -471,6 +511,35 @@ mux {
};
};
gcc: clock-controller@900000 {
compatible = "qcom,gcc-ipq8064", "syscon";
clocks = <&pxo_board>, <&cxo_board>;
clock-names = "pxo", "cxo";
reg = <0x00900000 0x4000>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
tsens: thermal-sensor@900000 {
compatible = "qcom,ipq8064-tsens";
nvmem-cells = <&tsens_calib>, <&tsens_calib_backup>;
nvmem-cell-names = "calib", "calib_backup";
interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "uplow";
#qcom,sensors = <11>;
#thermal-sensor-cells = <1>;
};
};
sfpb_mutex: hwlock@1200600 {
compatible = "qcom,sfpb-mutex";
reg = <0x01200600 0x100>;
#hwlock-cells = <1>;
};
intc: interrupt-controller@2000000 {
compatible = "qcom,msm-qgic2";
interrupt-controller;
@ -500,48 +569,200 @@ IRQ_TYPE_EDGE_RISING)>,
cpu-offset = <0x80000>;
};
l2cc: clock-controller@2011000 {
compatible = "qcom,kpss-gcc", "syscon";
reg = <0x02011000 0x1000>;
clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
clock-names = "pll8_vote", "pxo";
clock-output-names = "acpu_l2_aux";
};
acc0: clock-controller@2088000 {
compatible = "qcom,kpss-acc-v1";
reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
};
acc1: clock-controller@2098000 {
compatible = "qcom,kpss-acc-v1";
reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
};
adm_dma: dma-controller@18300000 {
compatible = "qcom,adm";
reg = <0x18300000 0x100000>;
interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>;
clock-names = "core", "iface";
resets = <&gcc ADM0_RESET>,
<&gcc ADM0_PBUS_RESET>,
<&gcc ADM0_C0_RESET>,
<&gcc ADM0_C1_RESET>,
<&gcc ADM0_C2_RESET>;
reset-names = "clk", "pbus", "c0", "c1", "c2";
qcom,ee = <0>;
status = "disabled";
};
saw0: regulator@2089000 {
compatible = "qcom,saw2";
reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
regulator;
};
acc1: clock-controller@2098000 {
compatible = "qcom,kpss-acc-v1";
reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
};
saw1: regulator@2099000 {
compatible = "qcom,saw2";
reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
regulator;
};
nss_common: syscon@03000000 {
compatible = "syscon";
reg = <0x03000000 0x0000FFFF>;
};
usb3_0: usb3@100f8800 {
compatible = "qcom,ipq8064-dwc3", "qcom,dwc3";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x100f8800 0x8000>;
clocks = <&gcc USB30_0_MASTER_CLK>;
clock-names = "core";
ranges;
resets = <&gcc USB30_0_MASTER_RESET>;
reset-names = "master";
status = "disabled";
dwc3_0: dwc3@10000000 {
compatible = "snps,dwc3";
reg = <0x10000000 0xcd00>;
interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
phys = <&hs_phy_0>, <&ss_phy_0>;
phy-names = "usb2-phy", "usb3-phy";
dr_mode = "host";
snps,dis_u3_susphy_quirk;
};
};
hs_phy_0: phy@100f8800 {
compatible = "qcom,ipq806x-usb-phy-hs";
reg = <0x100f8800 0x30>;
clocks = <&gcc USB30_0_UTMI_CLK>;
clock-names = "ref";
#phy-cells = <0>;
status = "disabled";
};
ss_phy_0: phy@100f8830 {
compatible = "qcom,ipq806x-usb-phy-ss";
reg = <0x100f8830 0x30>;
clocks = <&gcc USB30_0_MASTER_CLK>;
clock-names = "ref";
#phy-cells = <0>;
status = "disabled";
};
usb3_1: usb3@110f8800 {
compatible = "qcom,ipq8064-dwc3", "qcom,dwc3";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x110f8800 0x8000>;
clocks = <&gcc USB30_1_MASTER_CLK>;
clock-names = "core";
ranges;
resets = <&gcc USB30_1_MASTER_RESET>;
reset-names = "master";
status = "disabled";
dwc3_1: dwc3@11000000 {
compatible = "snps,dwc3";
reg = <0x11000000 0xcd00>;
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
phys = <&hs_phy_1>, <&ss_phy_1>;
phy-names = "usb2-phy", "usb3-phy";
dr_mode = "host";
snps,dis_u3_susphy_quirk;
};
};
hs_phy_1: phy@110f8800 {
compatible = "qcom,ipq806x-usb-phy-hs";
reg = <0x110f8800 0x30>;
clocks = <&gcc USB30_1_UTMI_CLK>;
clock-names = "ref";
#phy-cells = <0>;
status = "disabled";
};
ss_phy_1: phy@110f8830 {
compatible = "qcom,ipq806x-usb-phy-ss";
reg = <0x110f8830 0x30>;
clocks = <&gcc USB30_1_MASTER_CLK>;
clock-names = "ref";
#phy-cells = <0>;
status = "disabled";
};
sdcc3bam: dma-controller@12182000 {
compatible = "qcom,bam-v1.3.0";
reg = <0x12182000 0x8000>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc SDC3_H_CLK>;
clock-names = "bam_clk";
#dma-cells = <1>;
qcom,ee = <0>;
};
sdcc1bam: dma-controller@12402000 {
compatible = "qcom,bam-v1.3.0";
reg = <0x12402000 0x8000>;
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc SDC1_H_CLK>;
clock-names = "bam_clk";
#dma-cells = <1>;
qcom,ee = <0>;
};
amba: amba {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
sdcc3: mmc@12180000 {
compatible = "arm,pl18x", "arm,primecell";
arm,primecell-periphid = <0x00051180>;
status = "disabled";
reg = <0x12180000 0x2000>;
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "cmd_irq";
clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
clock-names = "mclk", "apb_pclk";
bus-width = <8>;
cap-sd-highspeed;
cap-mmc-highspeed;
max-frequency = <192000000>;
sd-uhs-sdr104;
sd-uhs-ddr50;
vqmmc-supply = <&vsdcc_fixed>;
dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
dma-names = "tx", "rx";
};
sdcc1: mmc@12400000 {
status = "disabled";
compatible = "arm,pl18x", "arm,primecell";
arm,primecell-periphid = <0x00051180>;
reg = <0x12400000 0x2000>;
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "cmd_irq";
clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
clock-names = "mclk", "apb_pclk";
bus-width = <8>;
max-frequency = <96000000>;
non-removable;
cap-sd-highspeed;
cap-mmc-highspeed;
mmc-ddr-1_8v;
vmmc-supply = <&vsdcc_fixed>;
dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
dma-names = "tx", "rx";
};
};
gsbi1: gsbi@12440000 {
compatible = "qcom,gsbi-v1.0.0";
reg = <0x12440000 0x100>;
@ -654,56 +875,6 @@ i2c@16380000 {
};
};
gsbi5: gsbi@1a200000 {
compatible = "qcom,gsbi-v1.0.0";
cell-index = <5>;
reg = <0x1a200000 0x100>;
clocks = <&gcc GSBI5_H_CLK>;
clock-names = "iface";
#address-cells = <1>;
#size-cells = <1>;
ranges;
status = "disabled";
syscon-tcsr = <&tcsr>;
gsbi5_serial: serial@1a240000 {
compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
reg = <0x1a240000 0x1000>,
<0x1a200000 0x1000>;
interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
clock-names = "core", "iface";
status = "disabled";
};
i2c@1a280000 {
compatible = "qcom,i2c-qup-v1.1.1";
reg = <0x1a280000 0x1000>;
interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
clock-names = "core", "iface";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
spi@1a280000 {
compatible = "qcom,spi-qup-v1.1.1";
reg = <0x1a280000 0x1000>;
interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
clock-names = "core", "iface";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
};
gsbi6: gsbi@16500000 {
compatible = "qcom,gsbi-v1.0.0";
reg = <0x16500000 0x100>;
@ -784,6 +955,82 @@ gsbi7_i2c: i2c@16680000 {
};
};
adm_dma: dma-controller@18300000 {
compatible = "qcom,adm";
reg = <0x18300000 0x100000>;
interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>;
clock-names = "core", "iface";
resets = <&gcc ADM0_RESET>,
<&gcc ADM0_PBUS_RESET>,
<&gcc ADM0_C0_RESET>,
<&gcc ADM0_C1_RESET>,
<&gcc ADM0_C2_RESET>;
reset-names = "clk", "pbus", "c0", "c1", "c2";
qcom,ee = <0>;
status = "disabled";
};
gsbi5: gsbi@1a200000 {
compatible = "qcom,gsbi-v1.0.0";
cell-index = <5>;
reg = <0x1a200000 0x100>;
clocks = <&gcc GSBI5_H_CLK>;
clock-names = "iface";
#address-cells = <1>;
#size-cells = <1>;
ranges;
status = "disabled";
syscon-tcsr = <&tcsr>;
gsbi5_serial: serial@1a240000 {
compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
reg = <0x1a240000 0x1000>,
<0x1a200000 0x1000>;
interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
clock-names = "core", "iface";
status = "disabled";
};
i2c@1a280000 {
compatible = "qcom,i2c-qup-v1.1.1";
reg = <0x1a280000 0x1000>;
interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
clock-names = "core", "iface";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
spi@1a280000 {
compatible = "qcom,spi-qup-v1.1.1";
reg = <0x1a280000 0x1000>;
interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
clock-names = "core", "iface";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
};
tcsr: syscon@1a400000 {
compatible = "qcom,tcsr-ipq8064", "syscon";
reg = <0x1a400000 0x100>;
};
rng@1a500000 {
compatible = "qcom,prng";
reg = <0x1a500000 0x200>;
@ -791,17 +1038,6 @@ rng@1a500000 {
clock-names = "core";
};
sata_phy: sata-phy@1b400000 {
compatible = "qcom,ipq806x-sata-phy";
reg = <0x1b400000 0x200>;
clocks = <&gcc SATA_PHY_CFG_CLK>;
clock-names = "cfg";
#phy-cells = <0>;
status = "disabled";
};
nand: nand-controller@1ac00000 {
compatible = "qcom,ipq806x-nand";
reg = <0x1ac00000 0x800>;
@ -824,113 +1060,17 @@ nand: nand-controller@1ac00000 {
status = "disabled";
};
sata: sata@29000000 {
compatible = "qcom,ipq806x-ahci", "generic-ahci";
reg = <0x29000000 0x180>;
sata_phy: sata-phy@1b400000 {
compatible = "qcom,ipq806x-sata-phy";
reg = <0x1b400000 0x200>;
interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc SATA_PHY_CFG_CLK>;
clock-names = "cfg";
clocks = <&gcc SFAB_SATA_S_H_CLK>,
<&gcc SATA_H_CLK>,
<&gcc SATA_A_CLK>,
<&gcc SATA_RXOOB_CLK>,
<&gcc SATA_PMALIVE_CLK>;
clock-names = "slave_face", "iface", "core",
"rxoob", "pmalive";
assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>;
assigned-clock-rates = <100000000>, <100000000>;
phys = <&sata_phy>;
phy-names = "sata-phy";
#phy-cells = <0>;
status = "disabled";
};
qcom,ssbi@500000 {
compatible = "qcom,ssbi";
reg = <0x00500000 0x1000>;
qcom,controller-type = "pmic-arbiter";
};
qfprom: qfprom@700000 {
compatible = "qcom,ipq8064-qfprom", "qcom,qfprom";
reg = <0x00700000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
speedbin_efuse: speedbin@c0 {
reg = <0xc0 0x4>;
};
tsens_calib: calib@400 {
reg = <0x400 0xb>;
};
tsens_calib_backup: calib_backup@410 {
reg = <0x410 0xb>;
};
};
gcc: clock-controller@900000 {
compatible = "qcom,gcc-ipq8064", "syscon";
clocks = <&pxo_board>, <&cxo_board>;
clock-names = "pxo", "cxo";
reg = <0x00900000 0x4000>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
tsens: thermal-sensor@900000 {
compatible = "qcom,ipq8064-tsens";
nvmem-cells = <&tsens_calib>, <&tsens_calib_backup>;
nvmem-cell-names = "calib", "calib_backup";
interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "uplow";
#qcom,sensors = <11>;
#thermal-sensor-cells = <1>;
};
};
rpm: rpm@108000 {
compatible = "qcom,rpm-ipq8064";
reg = <0x108000 0x1000>;
qcom,ipc = <&l2cc 0x8 2>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ack", "err", "wakeup";
clocks = <&gcc RPM_MSG_RAM_H_CLK>;
clock-names = "ram";
rpmcc: clock-controller {
compatible = "qcom,rpmcc-ipq806x", "qcom,rpmcc";
#clock-cells = <1>;
clocks = <&pxo_board>;
clock-names = "pxo";
};
};
tcsr: syscon@1a400000 {
compatible = "qcom,tcsr-ipq8064", "syscon";
reg = <0x1a400000 0x100>;
};
l2cc: clock-controller@2011000 {
compatible = "qcom,kpss-gcc", "syscon";
reg = <0x2011000 0x1000>;
clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
clock-names = "pll8_vote", "pxo";
clock-output-names = "acpu_l2_aux";
};
lcc: clock-controller@28000000 {
compatible = "qcom,lcc-ipq8064";
reg = <0x28000000 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
pcie0: pci@1b500000 {
compatible = "qcom,pcie-ipq8064";
reg = <0x1b500000 0x1000
@ -979,7 +1119,7 @@ pcie0: pci@1b500000 {
pinctrl-names = "default";
status = "disabled";
perst-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;
perst-gpios = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;
};
pcie1: pci@1b700000 {
@ -1030,7 +1170,7 @@ pcie1: pci@1b700000 {
pinctrl-names = "default";
status = "disabled";
perst-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
perst-gpios = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
};
pcie2: pci@1b900000 {
@ -1081,12 +1221,7 @@ pcie2: pci@1b900000 {
pinctrl-names = "default";
status = "disabled";
perst-gpio = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>;
};
nss_common: syscon@03000000 {
compatible = "syscon";
reg = <0x03000000 0x0000FFFF>;
perst-gpios = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>;
};
qsgmii_csr: syscon@1bb00000 {
@ -1094,10 +1229,48 @@ qsgmii_csr: syscon@1bb00000 {
reg = <0x1bb00000 0x000001FF>;
};
stmmac_axi_setup: stmmac-axi-config {
snps,wr_osr_lmt = <7>;
snps,rd_osr_lmt = <7>;
snps,blen = <16 0 0 0 0 0 0>;
lcc: clock-controller@28000000 {
compatible = "qcom,lcc-ipq8064";
reg = <0x28000000 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
lpass@28100000 {
compatible = "qcom,lpass-cpu";
status = "disabled";
clocks = <&lcc AHBIX_CLK>,
<&lcc MI2S_OSR_CLK>,
<&lcc MI2S_BIT_CLK>;
clock-names = "ahbix-clk",
"mi2s-osr-clk",
"mi2s-bit-clk";
interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "lpass-irq-lpaif";
reg = <0x28100000 0x10000>;
reg-names = "lpass-lpaif";
};
sata: sata@29000000 {
compatible = "qcom,ipq806x-ahci", "generic-ahci";
reg = <0x29000000 0x180>;
interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc SFAB_SATA_S_H_CLK>,
<&gcc SATA_H_CLK>,
<&gcc SATA_A_CLK>,
<&gcc SATA_RXOOB_CLK>,
<&gcc SATA_PMALIVE_CLK>;
clock-names = "slave_face", "iface", "core",
"rxoob", "pmalive";
assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>;
assigned-clock-rates = <100000000>, <100000000>;
phys = <&sata_phy>;
phy-names = "sata-phy";
status = "disabled";
};
gmac0: ethernet@37000000 {
@ -1195,179 +1368,5 @@ gmac3: ethernet@37600000 {
status = "disabled";
};
hs_phy_0: phy@100f8800 {
compatible = "qcom,ipq806x-usb-phy-hs";
reg = <0x100f8800 0x30>;
clocks = <&gcc USB30_0_UTMI_CLK>;
clock-names = "ref";
#phy-cells = <0>;
status = "disabled";
};
ss_phy_0: phy@100f8830 {
compatible = "qcom,ipq806x-usb-phy-ss";
reg = <0x100f8830 0x30>;
clocks = <&gcc USB30_0_MASTER_CLK>;
clock-names = "ref";
#phy-cells = <0>;
status = "disabled";
};
usb3_0: usb3@100f8800 {
compatible = "qcom,ipq8064-dwc3", "qcom,dwc3";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x100f8800 0x8000>;
clocks = <&gcc USB30_0_MASTER_CLK>;
clock-names = "core";
ranges;
resets = <&gcc USB30_0_MASTER_RESET>;
reset-names = "master";
status = "disabled";
dwc3_0: dwc3@10000000 {
compatible = "snps,dwc3";
reg = <0x10000000 0xcd00>;
interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
phys = <&hs_phy_0>, <&ss_phy_0>;
phy-names = "usb2-phy", "usb3-phy";
dr_mode = "host";
snps,dis_u3_susphy_quirk;
};
};
hs_phy_1: phy@110f8800 {
compatible = "qcom,ipq806x-usb-phy-hs";
reg = <0x110f8800 0x30>;
clocks = <&gcc USB30_1_UTMI_CLK>;
clock-names = "ref";
#phy-cells = <0>;
status = "disabled";
};
ss_phy_1: phy@110f8830 {
compatible = "qcom,ipq806x-usb-phy-ss";
reg = <0x110f8830 0x30>;
clocks = <&gcc USB30_1_MASTER_CLK>;
clock-names = "ref";
#phy-cells = <0>;
status = "disabled";
};
usb3_1: usb3@110f8800 {
compatible = "qcom,ipq8064-dwc3", "qcom,dwc3";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x110f8800 0x8000>;
clocks = <&gcc USB30_1_MASTER_CLK>;
clock-names = "core";
ranges;
resets = <&gcc USB30_1_MASTER_RESET>;
reset-names = "master";
status = "disabled";
dwc3_1: dwc3@11000000 {
compatible = "snps,dwc3";
reg = <0x11000000 0xcd00>;
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
phys = <&hs_phy_1>, <&ss_phy_1>;
phy-names = "usb2-phy", "usb3-phy";
dr_mode = "host";
snps,dis_u3_susphy_quirk;
};
};
vsdcc_fixed: vsdcc-regulator {
compatible = "regulator-fixed";
regulator-name = "SDCC Power";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
sdcc1bam: dma-controller@12402000 {
compatible = "qcom,bam-v1.3.0";
reg = <0x12402000 0x8000>;
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc SDC1_H_CLK>;
clock-names = "bam_clk";
#dma-cells = <1>;
qcom,ee = <0>;
};
sdcc3bam: dma-controller@12182000 {
compatible = "qcom,bam-v1.3.0";
reg = <0x12182000 0x8000>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc SDC3_H_CLK>;
clock-names = "bam_clk";
#dma-cells = <1>;
qcom,ee = <0>;
};
amba: amba {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
sdcc1: mmc@12400000 {
status = "disabled";
compatible = "arm,pl18x", "arm,primecell";
arm,primecell-periphid = <0x00051180>;
reg = <0x12400000 0x2000>;
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "cmd_irq";
clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
clock-names = "mclk", "apb_pclk";
bus-width = <8>;
max-frequency = <96000000>;
non-removable;
cap-sd-highspeed;
cap-mmc-highspeed;
mmc-ddr-1_8v;
vmmc-supply = <&vsdcc_fixed>;
dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
dma-names = "tx", "rx";
};
sdcc3: mmc@12180000 {
compatible = "arm,pl18x", "arm,primecell";
arm,primecell-periphid = <0x00051180>;
status = "disabled";
reg = <0x12180000 0x2000>;
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "cmd_irq";
clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
clock-names = "mclk", "apb_pclk";
bus-width = <8>;
cap-sd-highspeed;
cap-mmc-highspeed;
max-frequency = <192000000>;
sd-uhs-sdr104;
sd-uhs-ddr50;
vqmmc-supply = <&vsdcc_fixed>;
dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
dma-names = "tx", "rx";
};
};
sfpb_mutex: hwlock@1200600 {
compatible = "qcom,sfpb-mutex";
reg = <0x01200600 0x100>;
#hwlock-cells = <1>;
};
};
};

37
arch/arm/boot/dts/qcom-ipq8065-smb208.dtsi Normal file
View file

@ -0,0 +1,37 @@
// SPDX-License-Identifier: GPL-2.0
#include "qcom-ipq8065.dtsi"
&rpm {
smb208_regulators: regulators {
compatible = "qcom,rpm-smb208-regulators";
smb208_s1a: s1a {
regulator-min-microvolt = <1050000>;
regulator-max-microvolt = <1150000>;
qcom,switch-mode-frequency = <1200000>;
};
smb208_s1b: s1b {
regulator-min-microvolt = <1050000>;
regulator-max-microvolt = <1150000>;
qcom,switch-mode-frequency = <1200000>;
};
smb208_s2a: s2a {
regulator-min-microvolt = <775000>;
regulator-max-microvolt = <1275000>;
qcom,switch-mode-frequency = <1200000>;
};
smb208_s2b: s2b {
regulator-min-microvolt = <775000>;
regulator-max-microvolt = <1275000>;
qcom,switch-mode-frequency = <1200000>;
};
};
};

8
arch/arm/boot/dts/qcom-ipq8065.dtsi Normal file
View file

@ -0,0 +1,8 @@
// SPDX-License-Identifier: GPL-2.0
#include "qcom-ipq8064-v2.0.dtsi"
/ {
model = "Qualcomm Technologies, Inc. IPQ8065";
compatible = "qcom,ipq8065", "qcom,ipq8064";
};

4
arch/arm/boot/dts/qcom-msm8226-samsung-s3ve3g.dts
View file

@ -18,8 +18,6 @@ chosen {
};
};
&soc {
serial@f991f000 {
&blsp1_uart3 {
status = "ok";
};
};

103
arch/arm/boot/dts/qcom-msm8226.dtsi
View file

@ -8,6 +8,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-msm8974.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/reset/qcom,gcc-msm8974.h>
/ {
@ -44,13 +45,6 @@ scm {
};
};
tcsr_mutex: hwlock {
compatible = "qcom,tcsr-mutex";
syscon = <&tcsr_mutex_block 0 0x80>;
#hwlock-cells = <1>;
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
@ -60,6 +54,11 @@ smem_region: smem@3000000 {
reg = <0x3000000 0x100000>;
no-map;
};
adsp_region: adsp@dc00000 {
reg = <0x0dc00000 0x1900000>;
no-map;
};
};
smd {
@ -115,6 +114,31 @@ smem {
hwlocks = <&tcsr_mutex 3>;
};
smp2p-adsp {
compatible = "qcom,smp2p";
qcom,smem = <443>, <429>;
interrupt-parent = <&intc>;
interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
qcom,ipc = <&apcs 8 10>;
qcom,local-pid = <0>;
qcom,remote-pid = <2>;
adsp_smp2p_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,smem-state-cells = <1>;
};
adsp_smp2p_in: slave-kernel {
qcom,entry-name = "slave-kernel";
interrupt-controller;
#interrupt-cells = <2>;
};
};
soc: soc {
compatible = "simple-bus";
#address-cells = <1>;
@ -137,14 +161,14 @@ apcs: syscon@f9011000 {
sdhc_1: mmc@f9824900 {
compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4";
reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
reg-names = "hc_mem", "core_mem";
reg-names = "hc", "core";
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
clocks = <&gcc GCC_SDCC1_APPS_CLK>,
<&gcc GCC_SDCC1_AHB_CLK>,
clocks = <&gcc GCC_SDCC1_AHB_CLK>,
<&gcc GCC_SDCC1_APPS_CLK>,
<&xo_board>;
clock-names = "core", "iface", "xo";
clock-names = "iface", "core", "xo";
pinctrl-names = "default";
pinctrl-0 = <&sdhc1_default_state>;
status = "disabled";
@ -153,14 +177,14 @@ sdhc_1: mmc@f9824900 {
sdhc_2: mmc@f98a4900 {
compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4";
reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
reg-names = "hc_mem", "core_mem";
reg-names = "hc", "core";
interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
clocks = <&gcc GCC_SDCC2_APPS_CLK>,
<&gcc GCC_SDCC2_AHB_CLK>,
clocks = <&gcc GCC_SDCC2_AHB_CLK>,
<&gcc GCC_SDCC2_APPS_CLK>,
<&xo_board>;
clock-names = "core", "iface", "xo";
clock-names = "iface", "core", "xo";
pinctrl-names = "default";
pinctrl-0 = <&sdhc2_default_state>;
status = "disabled";
@ -169,14 +193,14 @@ sdhc_2: mmc@f98a4900 {
sdhc_3: mmc@f9864900 {
compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4";
reg = <0xf9864900 0x11c>, <0xf9864000 0x800>;
reg-names = "hc_mem", "core_mem";
reg-names = "hc", "core";
interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
clocks = <&gcc GCC_SDCC3_APPS_CLK>,
<&gcc GCC_SDCC3_AHB_CLK>,
clocks = <&gcc GCC_SDCC3_AHB_CLK>,
<&gcc GCC_SDCC3_APPS_CLK>,
<&xo_board>;
clock-names = "core", "iface", "xo";
clock-names = "iface", "core", "xo";
pinctrl-names = "default";
pinctrl-0 = <&sdhc3_default_state>;
status = "disabled";
@ -508,9 +532,44 @@ rpm_msg_ram: memory@fc428000 {
reg = <0xfc428000 0x4000>;
};
tcsr_mutex_block: syscon@fd484000 {
compatible = "syscon";
reg = <0xfd484000 0x2000>;
tcsr_mutex: hwlock@fd484000 {
compatible = "qcom,msm8226-tcsr-mutex", "qcom,tcsr-mutex";
reg = <0xfd484000 0x1000>;
#hwlock-cells = <1>;
};
adsp: remoteproc@fe200000 {
compatible = "qcom,msm8226-adsp-pil";
reg = <0xfe200000 0x100>;
interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
<&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
<&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
<&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
<&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
power-domains = <&rpmpd MSM8226_VDDCX>;
power-domain-names = "cx";
clocks = <&xo_board>;
clock-names = "xo";
memory-region = <&adsp_region>;
qcom,smem-states = <&adsp_smp2p_out 0>;
qcom,smem-state-names = "stop";
status = "disabled";
smd-edge {
interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
qcom,ipc = <&apcs 8 8>;
qcom,smd-edge = <1>;
label = "lpass";
};
};
};

37
arch/arm/boot/dts/qcom-msm8660-surf.dts
View file

@ -15,15 +15,6 @@ chosen {
stdout-path = "serial0:115200n8";
};
soc {
gsbi@19c00000 {
status = "okay";
qcom,mode = <GSBI_PROT_I2C_UART>;
serial@19c40000 {
status = "okay";
};
};
/* Temporary fixed regulator */
vsdcc_fixed: vsdcc-regulator {
compatible = "regulator-fixed";
@ -32,21 +23,15 @@ vsdcc_fixed: vsdcc-regulator {
regulator-max-microvolt = <2700000>;
regulator-always-on;
};
amba {
/* eMMC */
sdcc1: mmc@12400000 {
status = "okay";
vmmc-supply = <&vsdcc_fixed>;
};
/* External micro SD card */
sdcc3: mmc@12180000 {
&gsbi12 {
qcom,mode = <GSBI_PROT_I2C_UART>;
status = "okay";
vmmc-supply = <&vsdcc_fixed>;
};
};
};
&gsbi12_serial {
status = "okay";
};
&pm8058 {
@ -76,3 +61,15 @@ MATRIX_KEY(5, 4, KEY_MENU)
keypad,num-columns = <5>;
};
};
/* eMMC */
&sdcc1 {
vmmc-supply = <&vsdcc_fixed>;
status = "okay";
};
/* External micro SD card */
&sdcc3 {
vmmc-supply = <&vsdcc_fixed>;
status = "okay";
};

62
arch/arm/boot/dts/qcom-msm8660.dtsi
View file

@ -50,22 +50,25 @@ cpu-pmu {
};
clocks {
cxo_board {
cxo_board: cxo-board-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <19200000>;
clock-output-names = "cxo_board";
};
pxo_board: pxo_board {
pxo_board: pxo-board-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <27000000>;
clock-output-names = "pxo_board";
};
sleep_clk {
sleep-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
clock-output-names = "sleep_clk";
};
};
@ -129,6 +132,59 @@ gcc: clock-controller@900000 {
#power-domain-cells = <1>;
#reset-cells = <1>;
reg = <0x900000 0x4000>;
clocks = <&pxo_board>, <&cxo_board>;
clock-names = "pxo", "cxo";
};
gsbi1: gsbi@16000000 {
compatible = "qcom,gsbi-v1.0.0";
cell-index = <12>;
reg = <0x16000000 0x100>;
clocks = <&gcc GSBI1_H_CLK>;
clock-names = "iface";
#address-cells = <1>;
#size-cells = <1>;
ranges;
syscon-tcsr = <&tcsr>;
status = "disabled";
gsbi1_spi: spi@16080000 {
compatible = "qcom,spi-qup-v1.1.1";
reg = <0x16080000 0x1000>;
interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
clock-names = "core", "iface";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
};
gsbi3: gsbi@16200000 {
compatible = "qcom,gsbi-v1.0.0";
cell-index = <12>;
reg = <0x16200000 0x100>;
clocks = <&gcc GSBI3_H_CLK>;
clock-names = "iface";
#address-cells = <1>;
#size-cells = <1>;
ranges;
syscon-tcsr = <&tcsr>;
status = "disabled";
gsbi3_i2c: i2c@16280000 {
compatible = "qcom,i2c-qup-v1.1.1";
reg = <0x16280000 0x1000>;
interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GSBI3_QUP_CLK>, <&gcc GSBI3_H_CLK>;
clock-names = "core", "iface";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
};
gsbi6: gsbi@16500000 {

179
arch/arm/boot/dts/qcom-msm8960-cdp.dts
View file

@ -15,28 +15,98 @@ chosen {
stdout-path = "serial0:115200n8";
};
soc {
gsbi@16400000 {
regulators {
compatible = "simple-bus";
ext_l2: gpio-regulator@91 {
compatible = "regulator-fixed";
regulator-name = "ext_l2";
gpio = <&msmgpio 91 0>;
startup-delay-us = <10000>;
enable-active-high;
};
};
};
&gsbi1 {
qcom,mode = <GSBI_PROT_SPI>;
pinctrl-names = "default";
pinctrl-0 = <&spi1_default>;
status = "okay";
};
&gsbi1_spi {
status = "okay";
ethernet@0 {
compatible = "micrel,ks8851";
reg = <0>;
interrupt-parent = <&msmgpio>;
interrupts = <90 8>;
spi-max-frequency = <5400000>;
vdd-supply = <&ext_l2>;
vdd-io-supply = <&pm8921_lvs6>;
reset-gpios = <&msmgpio 89 0>;
};
};
&gsbi5 {
qcom,mode = <GSBI_PROT_I2C_UART>;
serial@16440000 {
status = "okay";
};
};
amba {
/* eMMC */
sdcc1: mmc@12400000 {
status = "okay";
};
/* External micro SD card */
sdcc3: mmc@12180000 {
&gsbi5_serial {
status = "okay";
};
&msmgpio {
spi1_default: spi1_default {
mux {
pins = "gpio6", "gpio7", "gpio9";
function = "gsbi1";
};
mosi {
pins = "gpio6";
drive-strength = <12>;
bias-disable;
};
miso {
pins = "gpio7";
drive-strength = <12>;
bias-disable;
};
cs {
pins = "gpio8";
drive-strength = <12>;
bias-disable;
output-low;
};
clk {
pins = "gpio9";
drive-strength = <12>;
bias-disable;
};
};
};
rpm@108000 {
&pmicintc {
keypad@148 {
linux,keymap = <
MATRIX_KEY(0, 0, KEY_VOLUMEUP)
MATRIX_KEY(0, 1, KEY_VOLUMEDOWN)
MATRIX_KEY(0, 2, KEY_CAMERA_FOCUS)
MATRIX_KEY(0, 3, KEY_CAMERA)
>;
keypad,num-rows = <1>;
keypad,num-columns = <5>;
};
};
&rpm {
regulators {
compatible = "qcom,rpm-pm8921-regulators";
vin_lvs1_3_6-supply = <&pm8921_s4>;
@ -272,83 +342,12 @@ pm8921_ncp: ncp {
};
};
gsbi@16000000 {
/* eMMC */
&sdcc1 {
status = "okay";
qcom,mode = <GSBI_PROT_SPI>;
pinctrl-names = "default";
pinctrl-0 = <&spi1_default>;
spi@16080000 {
};
/* External micro SD card */
&sdcc3 {
status = "okay";
ethernet@0 {
compatible = "micrel,ks8851";
reg = <0>;
interrupt-parent = <&msmgpio>;
interrupts = <90 8>;
spi-max-frequency = <5400000>;
vdd-supply = <&ext_l2>;
vdd-io-supply = <&pm8921_lvs6>;
reset-gpios = <&msmgpio 89 0>;
};
};
};
pinctrl@800000 {
spi1_default: spi1_default {
mux {
pins = "gpio6", "gpio7", "gpio9";
function = "gsbi1";
};
mosi {
pins = "gpio6";
drive-strength = <12>;
bias-disable;
};
miso {
pins = "gpio7";
drive-strength = <12>;
bias-disable;
};
cs {
pins = "gpio8";
drive-strength = <12>;
bias-disable;
output-low;
};
clk {
pins = "gpio9";
drive-strength = <12>;
bias-disable;
};
};
};
};
regulators {
compatible = "simple-bus";
ext_l2: gpio-regulator@91 {
compatible = "regulator-fixed";
regulator-name = "ext_l2";
gpio = <&msmgpio 91 0>;
startup-delay-us = <10000>;
enable-active-high;
};
};
};
&pmicintc {
keypad@148 {
linux,keymap = <
MATRIX_KEY(0, 0, KEY_VOLUMEUP)
MATRIX_KEY(0, 1, KEY_VOLUMEDOWN)
MATRIX_KEY(0, 2, KEY_CAMERA_FOCUS)
MATRIX_KEY(0, 3, KEY_CAMERA)
>;
keypad,num-rows = <1>;
keypad,num-columns = <5>;
};
};

45
arch/arm/boot/dts/qcom-msm8960.dtsi
View file

@ -3,6 +3,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-msm8960.h>
#include <dt-bindings/clock/qcom,lcc-msm8960.h>
#include <dt-bindings/mfd/qcom-rpm.h>
#include <dt-bindings/soc/qcom,gsbi.h>
@ -56,14 +57,14 @@ cpu-pmu {
};
clocks {
cxo_board {
cxo_board: cxo_board {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <19200000>;
clock-output-names = "cxo_board";
};
pxo_board {
pxo_board: pxo_board {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <27000000>;
@ -130,6 +131,10 @@ gcc: clock-controller@900000 {
#power-domain-cells = <1>;
#reset-cells = <1>;
reg = <0x900000 0x4000>;
clocks = <&cxo_board>,
<&pxo_board>,
<&lcc PLL4>;
clock-names = "cxo", "pxo", "pll4";
};
lcc: clock-controller@28000000 {
@ -137,6 +142,20 @@ lcc: clock-controller@28000000 {
reg = <0x28000000 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
clocks = <&pxo_board>,
<&gcc PLL4_VOTE>,
<0>,
<0>, <0>,
<0>, <0>,
<0>;
clock-names = "pxo",
"pll4_vote",
"mi2s_codec_clk",
"codec_i2s_mic_codec_clk",
"spare_i2s_mic_codec_clk",
"codec_i2s_spkr_codec_clk",
"spare_i2s_spkr_codec_clk",
"pcm_codec_clk";
};
clock-controller@4000000 {
@ -145,6 +164,22 @@ clock-controller@4000000 {
#clock-cells = <1>;
#power-domain-cells = <1>;
#reset-cells = <1>;
clocks = <&pxo_board>,
<&gcc PLL3>,
<&gcc PLL8_VOTE>,
<0>,
<0>,
<0>,
<0>,
<0>;
clock-names = "pxo",
"pll3",
"pll8_vote",
"dsi1pll",
"dsi1pllbyte",
"dsi2pll",
"dsi2pllbyte",
"hdmipll";
};
l2cc: clock-controller@2011000 {
@ -152,7 +187,7 @@ l2cc: clock-controller@2011000 {
reg = <0x2011000 0x1000>;
};
rpm@108000 {
rpm: rpm@108000 {
compatible = "qcom,rpm-msm8960";
reg = <0x108000 0x1000>;
qcom,ipc = <&l2cc 0x8 2>;
@ -307,7 +342,7 @@ tcsr: syscon@1a400000 {
reg = <0x1a400000 0x100>;
};
gsbi@16000000 {
gsbi1: gsbi@16000000 {
compatible = "qcom,gsbi-v1.0.0";
cell-index = <1>;
reg = <0x16000000 0x100>;
@ -317,7 +352,7 @@ gsbi@16000000 {
#size-cells = <1>;
ranges;
spi@16080000 {
gsbi1_spi: spi@16080000 {
compatible = "qcom,spi-qup-v1.1.1";
#address-cells = <1>;
#size-cells = <0>;

2
arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts
View file

@ -175,7 +175,7 @@ i2c-gate {
ak8963@f {
compatible = "asahi-kasei,ak8963";
reg = <0x0f>;
gpios = <&tlmm 67 0>;
gpios = <&tlmm 67 GPIO_ACTIVE_HIGH>;
vid-supply = <&pm8941_lvs1>;
vdd-supply = <&pm8941_l17>;
};

29
arch/arm/boot/dts/qcom-msm8974.dtsi
View file

@ -439,14 +439,14 @@ acc3: clock-controller@f90b8000 {
sdhc_1: mmc@f9824900 {
compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
reg-names = "hc_mem", "core_mem";
reg-names = "hc", "core";
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
clocks = <&gcc GCC_SDCC1_APPS_CLK>,
<&gcc GCC_SDCC1_AHB_CLK>,
clocks = <&gcc GCC_SDCC1_AHB_CLK>,
<&gcc GCC_SDCC1_APPS_CLK>,
<&xo_board>;
clock-names = "core", "iface", "xo";
clock-names = "iface", "core", "xo";
bus-width = <8>;
non-removable;
@ -456,14 +456,14 @@ sdhc_1: mmc@f9824900 {
sdhc_3: mmc@f9864900 {
compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
reg = <0xf9864900 0x11c>, <0xf9864000 0x800>;
reg-names = "hc_mem", "core_mem";
reg-names = "hc", "core";
interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
clocks = <&gcc GCC_SDCC3_APPS_CLK>,
<&gcc GCC_SDCC3_AHB_CLK>,
clocks = <&gcc GCC_SDCC3_AHB_CLK>,
<&gcc GCC_SDCC3_APPS_CLK>,
<&xo_board>;
clock-names = "core", "iface", "xo";
clock-names = "iface", "core", "xo";
bus-width = <4>;
#address-cells = <1>;
@ -475,14 +475,14 @@ sdhc_3: mmc@f9864900 {
sdhc_2: mmc@f98a4900 {
compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
reg-names = "hc_mem", "core_mem";
reg-names = "hc", "core";
interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
clocks = <&gcc GCC_SDCC2_APPS_CLK>,
<&gcc GCC_SDCC2_AHB_CLK>,
clocks = <&gcc GCC_SDCC2_AHB_CLK>,
<&gcc GCC_SDCC2_APPS_CLK>,
<&xo_board>;
clock-names = "core", "iface", "xo";
clock-names = "iface", "core", "xo";
bus-width = <4>;
#address-cells = <1>;
@ -762,6 +762,11 @@ wifi {
};
};
sram@fc190000 {
compatible = "qcom,msm8974-rpm-stats";
reg = <0xfc190000 0x10000>;
};
etf@fc307000 {
compatible = "arm,coresight-tmc", "arm,primecell";
reg = <0xfc307000 0x1000>;

6
arch/arm/boot/dts/qcom-msm8974pro.dtsi
View file

@ -10,10 +10,10 @@ &gpu {
};
&sdhc_1 {
clocks = <&gcc GCC_SDCC1_APPS_CLK>,
<&gcc GCC_SDCC1_AHB_CLK>,
clocks = <&gcc GCC_SDCC1_AHB_CLK>,
<&gcc GCC_SDCC1_APPS_CLK>,
<&xo_board>,
<&gcc GCC_SDCC1_CDCCAL_FF_CLK>,
<&gcc GCC_SDCC1_CDCCAL_SLEEP_CLK>;
clock-names = "core", "iface", "xo", "cal", "sleep";
clock-names = "iface", "core", "xo", "cal", "sleep";
};

4
arch/arm/boot/dts/qcom-pm8941.dtsi
View file

@ -93,7 +93,7 @@ pm8941_temp: temp-alarm@2400 {
#thermal-sensor-cells = <0>;
};
pm8941_vadc: vadc@3100 {
pm8941_vadc: adc@3100 {
compatible = "qcom,spmi-vadc";
reg = <0x3100>;
interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
@ -144,7 +144,7 @@ pm8941_1: pm8941@1 {
#address-cells = <1>;
#size-cells = <0>;
pm8941_lpg: lpg {
pm8941_lpg: pwm {
compatible = "qcom,pm8941-lpg";
#address-cells = <1>;

2
arch/arm/boot/dts/qcom-pma8084.dtsi
View file

@ -56,7 +56,7 @@ pma8084_temp: temp-alarm@2400 {
io-channel-names = "thermal";
};
pma8084_vadc: vadc@3100 {
pma8084_vadc: adc@3100 {
compatible = "qcom,spmi-vadc";
reg = <0x3100>;
interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;

2
arch/arm/boot/dts/qcom-pmx55.dtsi
View file

@ -16,7 +16,7 @@ pmic@8 {
#address-cells = <1>;
#size-cells = <0>;
power-on@800 {
pon@800 {
compatible = "qcom,pm8916-pon";
reg = <0x0800>;

2
arch/arm/boot/dts/qcom-sdx65.dtsi
View file

@ -334,7 +334,7 @@ glink-edge {
sdhc_1: mmc@8804000 {
compatible = "qcom,sdx65-sdhci", "qcom,sdhci-msm-v5";
reg = <0x08804000 0x1000>;
reg-names = "hc_mem";
reg-names = "hc";
interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";