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ARM: tegra: apalis_t30: annotate/clean-up pcie controller/port nodes

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Annotate PCIe port nodes and clean-up PCIe controller/port status' with
respect to carrier board vs. module level device trees. As port 3
connects to the on-module Gigabit Ethernet MACPHY it is always enabled
together with the PCIe controller itself.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
Marcel Ziswiler 2018-08-31 18:37:47 +02:00 committed by Thierry Reding
parent 4f6b07a278
commit 7890d7856a
2 changed files with 5 additions and 6 deletions
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6
arch/arm/boot/dts/tegra30-apalis-eval.dts
View file

@ -23,8 +23,6 @@ chosen {
};
pcie@3000 {
status = "okay";
pci@1,0 {
status = "okay";
};
@ -32,10 +30,6 @@ pci@1,0 {
pci@2,0 {
status = "okay";
};
pci@3,0 {
status = "okay";
};
};
host1x@50000000 {

5
arch/arm/boot/dts/tegra30-apalis.dtsi
View file

@ -15,6 +15,7 @@ memory@80000000 {
};
pcie@3000 {
status = "okay";
avdd-pexa-supply = <&vdd2_reg>;
avdd-pexb-supply = <&vdd2_reg>;
avdd-pex-pll-supply = <&vdd2_reg>;
@ -24,15 +25,19 @@ pcie@3000 {
vdd-pexa-supply = <&vdd2_reg>;
vdd-pexb-supply = <&vdd2_reg>;
/* Apalis type specific */
pci@1,0 {
nvidia,num-lanes = <4>;
};
/* Apalis PCIe */
pci@2,0 {
nvidia,num-lanes = <1>;
};
/* I210/I211 Gigabit Ethernet Controller (on-module) */
pci@3,0 {
status = "okay";
nvidia,num-lanes = <1>;
pcie@0 {
reg = <0 0 0 0 0>;