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ARM: davinci: psc: fix incorrect offsets
Seperate PDSTAT and PDCTL registers are defined for domain 0 and domain 1 where as the code always reads the domain 0 PDSTAT register and domain 1 PDCTL register. Fix this issue. While at it, introduce usage of macros for register masks to improve readability. Reviewed-by: Sergei Shtylyov <sshtylyov@mvista.com> Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com>
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parent
8f9a0981ac
commit
78b838252f
2 changed files with 11 additions and 9 deletions
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@ -233,7 +233,7 @@
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#define PTCMD 0x120
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#define PTSTAT 0x128
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#define PDSTAT 0x200
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#define PDCTL1 0x304
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#define PDCTL 0x300
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#define MDSTAT 0x800
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#define MDCTL 0xA00
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@ -246,6 +246,8 @@
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#define MDSTAT_STATE_MASK 0x3f
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#define PDSTAT_STATE_MASK 0x1f
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#define MDCTL_FORCE BIT(31)
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#define PDCTL_NEXT BIT(1)
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#define PDCTL_EPCGOOD BIT(8)
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#ifndef __ASSEMBLER__
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@ -52,7 +52,7 @@ int __init davinci_psc_is_clk_active(unsigned int ctlr, unsigned int id)
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void davinci_psc_config(unsigned int domain, unsigned int ctlr,
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unsigned int id, bool enable, u32 flags)
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{
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u32 epcpr, ptcmd, ptstat, pdstat, pdctl1, mdstat, mdctl;
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u32 epcpr, ptcmd, ptstat, pdstat, pdctl, mdstat, mdctl;
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void __iomem *psc_base;
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struct davinci_soc_info *soc_info = &davinci_soc_info;
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u32 next_state = PSC_STATE_ENABLE;
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@ -79,11 +79,11 @@ void davinci_psc_config(unsigned int domain, unsigned int ctlr,
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mdctl |= MDCTL_FORCE;
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__raw_writel(mdctl, psc_base + MDCTL + 4 * id);
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pdstat = __raw_readl(psc_base + PDSTAT);
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pdstat = __raw_readl(psc_base + PDSTAT + 4 * domain);
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if ((pdstat & PDSTAT_STATE_MASK) == 0) {
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pdctl1 = __raw_readl(psc_base + PDCTL1);
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pdctl1 |= 0x1;
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__raw_writel(pdctl1, psc_base + PDCTL1);
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pdctl = __raw_readl(psc_base + PDCTL + 4 * domain);
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pdctl |= PDCTL_NEXT;
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__raw_writel(pdctl, psc_base + PDCTL + 4 * domain);
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ptcmd = 1 << domain;
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__raw_writel(ptcmd, psc_base + PTCMD);
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@ -92,9 +92,9 @@ void davinci_psc_config(unsigned int domain, unsigned int ctlr,
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epcpr = __raw_readl(psc_base + EPCPR);
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} while ((((epcpr >> domain) & 1) == 0));
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pdctl1 = __raw_readl(psc_base + PDCTL1);
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pdctl1 |= 0x100;
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__raw_writel(pdctl1, psc_base + PDCTL1);
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pdctl = __raw_readl(psc_base + PDCTL + 4 * domain);
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pdctl |= PDCTL_EPCGOOD;
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__raw_writel(pdctl, psc_base + PDCTL + 4 * domain);
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} else {
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ptcmd = 1 << domain;
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__raw_writel(ptcmd, psc_base + PTCMD);
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