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ARM: dts: stm32: Fix PHY post-reset delay on Avenger96
[ Upstream commitef2d907088
] Per KSZ9031RNX PHY datasheet FIGURE 7-5: POWER-UP/POWER-DOWN/RESET TIMING Note 2: After the de-assertion of reset, wait a minimum of 100 μs before starting programming on the MIIM (MDC/MDIO) interface. Add 1ms post-reset delay to guarantee this figure. Fixes:010ca9fe50
("ARM: dts: stm32: Add missing ethernet PHY reset on AV96") Signed-off-by: Marek Vasut <marex@denx.de> Cc: Alexandre Torgue <alexandre.torgue@foss.st.com> Cc: Patrice Chotard <patrice.chotard@foss.st.com> Cc: Patrick Delaunay <patrick.delaunay@foss.st.com> Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
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@ -141,6 +141,7 @@ mdio0 {
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compatible = "snps,dwmac-mdio";
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reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>;
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reset-delay-us = <1000>;
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reset-post-delay-us = <1000>;
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phy0: ethernet-phy@7 {
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reg = <7>;
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