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iommu/vt-d: Prepare for multiple DMA domain types
In preparation for the strict vs. non-strict decision for DMA domains to be expressed in the domain type, make sure we expose our flush queue awareness by accepting the new domain type, and test the specific feature flag where we want to identify DMA domains in general. The DMA ops reset/setup can simply be made unconditional, since iommu-dma already knows only to touch DMA domains. Reviewed-by: Lu Baolu <baolu.lu@linux.intel.com> Signed-off-by: Robin Murphy <robin.murphy@arm.com> Link: https://lore.kernel.org/r/31a8ef868d593a2f3826a6a120edee81815375a7.1628682049.git.robin.murphy@arm.com Signed-off-by: Joerg Roedel <jroedel@suse.de>
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78ca078459
1 changed files with 6 additions and 9 deletions
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@ -582,7 +582,7 @@ struct intel_iommu *domain_get_iommu(struct dmar_domain *domain)
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int iommu_id;
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int iommu_id;
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/* si_domain and vm domain should not get here. */
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/* si_domain and vm domain should not get here. */
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if (WARN_ON(domain->domain.type != IOMMU_DOMAIN_DMA))
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if (WARN_ON(!iommu_is_dma_domain(&domain->domain)))
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return NULL;
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return NULL;
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for_each_domain_iommu(iommu_id, domain)
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for_each_domain_iommu(iommu_id, domain)
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@ -1034,7 +1034,7 @@ static struct dma_pte *pfn_to_dma_pte(struct dmar_domain *domain,
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pteval = ((uint64_t)virt_to_dma_pfn(tmp_page) << VTD_PAGE_SHIFT) | DMA_PTE_READ | DMA_PTE_WRITE;
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pteval = ((uint64_t)virt_to_dma_pfn(tmp_page) << VTD_PAGE_SHIFT) | DMA_PTE_READ | DMA_PTE_WRITE;
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if (domain_use_first_level(domain)) {
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if (domain_use_first_level(domain)) {
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pteval |= DMA_FL_PTE_XD | DMA_FL_PTE_US;
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pteval |= DMA_FL_PTE_XD | DMA_FL_PTE_US;
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if (domain->domain.type == IOMMU_DOMAIN_DMA)
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if (iommu_is_dma_domain(&domain->domain))
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pteval |= DMA_FL_PTE_ACCESS;
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pteval |= DMA_FL_PTE_ACCESS;
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}
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}
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if (cmpxchg64(&pte->val, 0ULL, pteval))
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if (cmpxchg64(&pte->val, 0ULL, pteval))
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@ -2345,7 +2345,7 @@ __domain_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
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if (domain_use_first_level(domain)) {
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if (domain_use_first_level(domain)) {
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attr |= DMA_FL_PTE_XD | DMA_FL_PTE_US;
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attr |= DMA_FL_PTE_XD | DMA_FL_PTE_US;
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if (domain->domain.type == IOMMU_DOMAIN_DMA) {
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if (iommu_is_dma_domain(&domain->domain)) {
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attr |= DMA_FL_PTE_ACCESS;
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attr |= DMA_FL_PTE_ACCESS;
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if (prot & DMA_PTE_WRITE)
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if (prot & DMA_PTE_WRITE)
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attr |= DMA_FL_PTE_DIRTY;
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attr |= DMA_FL_PTE_DIRTY;
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@ -4528,6 +4528,7 @@ static struct iommu_domain *intel_iommu_domain_alloc(unsigned type)
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switch (type) {
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switch (type) {
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case IOMMU_DOMAIN_DMA:
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case IOMMU_DOMAIN_DMA:
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case IOMMU_DOMAIN_DMA_FQ:
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case IOMMU_DOMAIN_UNMANAGED:
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case IOMMU_DOMAIN_UNMANAGED:
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dmar_domain = alloc_domain(0);
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dmar_domain = alloc_domain(0);
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if (!dmar_domain) {
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if (!dmar_domain) {
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@ -5197,12 +5198,8 @@ static void intel_iommu_release_device(struct device *dev)
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static void intel_iommu_probe_finalize(struct device *dev)
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static void intel_iommu_probe_finalize(struct device *dev)
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{
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{
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struct iommu_domain *domain = iommu_get_domain_for_dev(dev);
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set_dma_ops(dev, NULL);
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iommu_setup_dma_ops(dev, 0, U64_MAX);
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if (domain && domain->type == IOMMU_DOMAIN_DMA)
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iommu_setup_dma_ops(dev, 0, U64_MAX);
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else
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set_dma_ops(dev, NULL);
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}
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}
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static void intel_iommu_get_resv_regions(struct device *device,
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static void intel_iommu_get_resv_regions(struct device *device,
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