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ARM: OMAP2+: dpll: Add missing soc_is_am33xx() check for common functions
Add missing soc_is_am33xx() check for DPLL common control & clock related functions, without this dpll programmability would be broken for am33xx family of devices. Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com> Cc: Rajendra Nayak <rnayak@ti.com> Cc: Paul Walmsley <paul@pwsan.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
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parent
a2cfc509bc
commit
78da264019
2 changed files with 4 additions and 4 deletions
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@ -211,7 +211,7 @@ void omap2_init_dpll_parent(struct clk *clk)
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if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||
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v == OMAP3XXX_EN_DPLL_FRBYPASS)
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clk_reparent(clk, dd->clk_bypass);
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} else if (cpu_is_omap44xx()) {
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} else if (soc_is_am33xx() || cpu_is_omap44xx()) {
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if (v == OMAP4XXX_EN_DPLL_LPBYPASS ||
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v == OMAP4XXX_EN_DPLL_FRBYPASS ||
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v == OMAP4XXX_EN_DPLL_MNBYPASS)
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@ -257,7 +257,7 @@ u32 omap2_get_dpll_rate(struct clk *clk)
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if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||
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v == OMAP3XXX_EN_DPLL_FRBYPASS)
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return dd->clk_bypass->rate;
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} else if (cpu_is_omap44xx()) {
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} else if (soc_is_am33xx() || cpu_is_omap44xx()) {
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if (v == OMAP4XXX_EN_DPLL_LPBYPASS ||
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v == OMAP4XXX_EN_DPLL_FRBYPASS ||
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v == OMAP4XXX_EN_DPLL_MNBYPASS)
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@ -311,7 +311,7 @@ static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel)
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* Set jitter correction. No jitter correction for OMAP4 and 3630
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* since freqsel field is no longer present
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*/
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if (!cpu_is_omap44xx() && !cpu_is_omap3630()) {
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if (!soc_is_am33xx() && !cpu_is_omap44xx() && !cpu_is_omap3630()) {
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v = __raw_readl(dd->control_reg);
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v &= ~dd->freqsel_mask;
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v |= freqsel << __ffs(dd->freqsel_mask);
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@ -471,7 +471,7 @@ int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
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return -EINVAL;
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/* No freqsel on OMAP4 and OMAP3630 */
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if (!cpu_is_omap44xx() && !cpu_is_omap3630()) {
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if (!soc_is_am33xx() && !cpu_is_omap44xx() && !cpu_is_omap3630()) {
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freqsel = _omap3_dpll_compute_freqsel(clk,
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dd->last_rounded_n);
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if (!freqsel)
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