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iommu/vt-d: Remove global page support in devTLB flush
Global pages support is removed from VT-d spec 3.0 for dev TLB invalidation. This patch is to remove the bits for vSVA. Similar change already made for the native SVA. See the link below. Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com> Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> Link: https://lore.kernel.org/linux-iommu/20190830142919.GE11578@8bytes.org/T/ Link: https://lore.kernel.org/r/20200724014925.15523-3-baolu.lu@linux.intel.com Signed-off-by: Joerg Roedel <jroedel@suse.de>
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3 changed files with 4 additions and 7 deletions
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@ -1438,8 +1438,7 @@ void qi_flush_piotlb(struct intel_iommu *iommu, u16 did, u32 pasid, u64 addr,
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/* PASID-based device IOTLB Invalidate */
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/* PASID-based device IOTLB Invalidate */
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void qi_flush_dev_iotlb_pasid(struct intel_iommu *iommu, u16 sid, u16 pfsid,
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void qi_flush_dev_iotlb_pasid(struct intel_iommu *iommu, u16 sid, u16 pfsid,
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u32 pasid, u16 qdep, u64 addr,
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u32 pasid, u16 qdep, u64 addr, unsigned int size_order)
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unsigned int size_order, u64 granu)
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{
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{
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unsigned long mask = 1UL << (VTD_PAGE_SHIFT + size_order - 1);
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unsigned long mask = 1UL << (VTD_PAGE_SHIFT + size_order - 1);
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struct qi_desc desc = {.qw1 = 0, .qw2 = 0, .qw3 = 0};
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struct qi_desc desc = {.qw1 = 0, .qw2 = 0, .qw3 = 0};
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@ -1447,7 +1446,6 @@ void qi_flush_dev_iotlb_pasid(struct intel_iommu *iommu, u16 sid, u16 pfsid,
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desc.qw0 = QI_DEV_EIOTLB_PASID(pasid) | QI_DEV_EIOTLB_SID(sid) |
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desc.qw0 = QI_DEV_EIOTLB_PASID(pasid) | QI_DEV_EIOTLB_SID(sid) |
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QI_DEV_EIOTLB_QDEP(qdep) | QI_DEIOTLB_TYPE |
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QI_DEV_EIOTLB_QDEP(qdep) | QI_DEIOTLB_TYPE |
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QI_DEV_IOTLB_PFSID(pfsid);
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QI_DEV_IOTLB_PFSID(pfsid);
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desc.qw1 = QI_DEV_EIOTLB_GLOB(granu);
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/*
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/*
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* If S bit is 0, we only flush a single page. If S bit is set,
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* If S bit is 0, we only flush a single page. If S bit is set,
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@ -5474,7 +5474,7 @@ intel_iommu_sva_invalidate(struct iommu_domain *domain, struct device *dev,
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info->pfsid, pasid,
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info->pfsid, pasid,
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info->ats_qdep,
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info->ats_qdep,
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inv_info->addr_info.addr,
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inv_info->addr_info.addr,
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size, granu);
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size);
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break;
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break;
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case IOMMU_CACHE_INV_TYPE_DEV_IOTLB:
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case IOMMU_CACHE_INV_TYPE_DEV_IOTLB:
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if (info->ats_enabled)
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if (info->ats_enabled)
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@ -5482,7 +5482,7 @@ intel_iommu_sva_invalidate(struct iommu_domain *domain, struct device *dev,
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info->pfsid, pasid,
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info->pfsid, pasid,
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info->ats_qdep,
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info->ats_qdep,
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inv_info->addr_info.addr,
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inv_info->addr_info.addr,
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size, granu);
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size);
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else
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else
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pr_warn_ratelimited("Passdown device IOTLB flush w/o ATS!\n");
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pr_warn_ratelimited("Passdown device IOTLB flush w/o ATS!\n");
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break;
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break;
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@ -381,7 +381,6 @@ enum {
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#define QI_DEV_EIOTLB_ADDR(a) ((u64)(a) & VTD_PAGE_MASK)
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#define QI_DEV_EIOTLB_ADDR(a) ((u64)(a) & VTD_PAGE_MASK)
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#define QI_DEV_EIOTLB_SIZE (((u64)1) << 11)
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#define QI_DEV_EIOTLB_SIZE (((u64)1) << 11)
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#define QI_DEV_EIOTLB_GLOB(g) ((u64)(g) & 0x1)
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#define QI_DEV_EIOTLB_PASID(p) ((u64)((p) & 0xfffff) << 32)
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#define QI_DEV_EIOTLB_PASID(p) ((u64)((p) & 0xfffff) << 32)
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#define QI_DEV_EIOTLB_SID(sid) ((u64)((sid) & 0xffff) << 16)
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#define QI_DEV_EIOTLB_SID(sid) ((u64)((sid) & 0xffff) << 16)
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#define QI_DEV_EIOTLB_QDEP(qd) ((u64)((qd) & 0x1f) << 4)
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#define QI_DEV_EIOTLB_QDEP(qd) ((u64)((qd) & 0x1f) << 4)
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@ -705,7 +704,7 @@ void qi_flush_piotlb(struct intel_iommu *iommu, u16 did, u32 pasid, u64 addr,
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void qi_flush_dev_iotlb_pasid(struct intel_iommu *iommu, u16 sid, u16 pfsid,
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void qi_flush_dev_iotlb_pasid(struct intel_iommu *iommu, u16 sid, u16 pfsid,
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u32 pasid, u16 qdep, u64 addr,
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u32 pasid, u16 qdep, u64 addr,
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unsigned int size_order, u64 granu);
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unsigned int size_order);
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void qi_flush_pasid_cache(struct intel_iommu *iommu, u16 did, u64 granu,
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void qi_flush_pasid_cache(struct intel_iommu *iommu, u16 did, u64 granu,
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int pasid);
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int pasid);
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