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Blackfin: simplify the do_flush macro
Simplify the do_flush macro now that we don't need to take into account a second instruction being used together. Signed-off-by: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Bryan Wu <cooloney@kernel.org>
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1 changed files with 15 additions and 15 deletions
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@ -15,6 +15,13 @@
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.text
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/* 05000443 - IFLUSH cannot be last instruction in hardware loop */
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#if ANOMALY_05000443
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# define BROK_FLUSH_INST "IFLUSH"
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#else
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# define BROK_FLUSH_INST "no anomaly! yeah!"
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#endif
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/* Since all L1 caches work the same way, we use the same method for flushing
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* them. Only the actual flush instruction differs. We write this in asm as
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* GCC can be hard to coax into writing nice hardware loops.
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@ -23,7 +30,7 @@
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* R0 = start address
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* R1 = end address
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*/
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.macro do_flush flushins:req optflushins optnopins label
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.macro do_flush flushins:req label
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R2 = -L1_CACHE_BYTES;
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@ -44,22 +51,15 @@
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\label :
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.endif
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P0 = R0;
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LSETUP (1f, 2f) LC1 = P1;
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1:
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.ifnb \optflushins
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\optflushins [P0];
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.endif
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#if ANOMALY_05000443
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.ifb \optnopins
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2:
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.endif
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.ifeqs "\flushins", BROK_FLUSH_INST
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\flushins [P0++];
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.ifnb \optnopins
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2: \optnopins;
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.endif
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#else
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2: nop;
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.else
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2: \flushins [P0++];
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#endif
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.endif
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RTS;
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.endm
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@ -77,7 +77,7 @@ ENTRY(_blackfin_icache_flush_range)
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*/
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P0 = R0;
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IFLUSH[P0];
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do_flush IFLUSH, , nop
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do_flush IFLUSH
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ENDPROC(_blackfin_icache_flush_range)
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/* Throw away all D-cached data in specified region without any obligation to
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@ -91,7 +91,7 @@ ENDPROC(_blackfin_dcache_invalidate_range)
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/* Flush all data cache lines assocoiated with this memory area */
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ENTRY(_blackfin_dcache_flush_range)
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do_flush FLUSH, , , .Ldfr
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do_flush FLUSH, .Ldfr
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ENDPROC(_blackfin_dcache_flush_range)
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/* Our headers convert the page structure to an address, so just need to flush
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