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drm/amd/display: Add DCN3 Support in DM (v2)
Handle DCN3 in amdgpu_dm v2: fix num_pkrs handling Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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5 changed files with 80 additions and 0 deletions
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@ -94,6 +94,10 @@
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#define FIRMWARE_RENOIR_DMUB "amdgpu/renoir_dmcub.bin"
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MODULE_FIRMWARE(FIRMWARE_RENOIR_DMUB);
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#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
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#define FIRMWARE_SIENNA_CICHLID_DMUB "amdgpu/sienna_cichlid_dmcub.bin"
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MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID_DMUB);
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#endif
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#define FIRMWARE_RAVEN_DMCU "amdgpu/raven_dmcu.bin"
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MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU);
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@ -1070,6 +1074,9 @@ static int load_dmcu_fw(struct amdgpu_device *adev)
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case CHIP_NAVI10:
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case CHIP_NAVI14:
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case CHIP_RENOIR:
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#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
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case CHIP_SIENNA_CICHLID:
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#endif
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return 0;
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case CHIP_NAVI12:
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fw_name_dmcu = FIRMWARE_NAVI12_DMCU;
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@ -1166,6 +1173,12 @@ static int dm_dmub_sw_init(struct amdgpu_device *adev)
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dmub_asic = DMUB_ASIC_DCN21;
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fw_name_dmub = FIRMWARE_RENOIR_DMUB;
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break;
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#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
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case CHIP_SIENNA_CICHLID:
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dmub_asic = DMUB_ASIC_DCN30;
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fw_name_dmub = FIRMWARE_SIENNA_CICHLID_DMUB;
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break;
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#endif
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default:
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/* ASIC doesn't support DMUB. */
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@ -3205,6 +3218,9 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
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case CHIP_NAVI10:
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case CHIP_NAVI14:
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case CHIP_RENOIR:
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#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
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case CHIP_SIENNA_CICHLID:
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#endif
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if (dcn10_register_irq_handlers(dm->adev)) {
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DRM_ERROR("DM: Failed to initialize IRQ\n");
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goto fail;
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@ -3359,6 +3375,9 @@ static int dm_early_init(void *handle)
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#endif
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case CHIP_NAVI10:
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case CHIP_NAVI12:
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#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
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case CHIP_SIENNA_CICHLID:
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#endif
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adev->mode_info.num_crtc = 6;
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adev->mode_info.num_hpd = 6;
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adev->mode_info.num_dig = 6;
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@ -3679,6 +3698,9 @@ fill_plane_buffer_attributes(struct amdgpu_device *adev,
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adev->asic_type == CHIP_NAVI10 ||
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adev->asic_type == CHIP_NAVI14 ||
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adev->asic_type == CHIP_NAVI12 ||
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#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
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adev->asic_type == CHIP_SIENNA_CICHLID ||
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#endif
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adev->asic_type == CHIP_RENOIR ||
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adev->asic_type == CHIP_RAVEN) {
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/* Fill GFX9 params */
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@ -3698,6 +3720,11 @@ fill_plane_buffer_attributes(struct amdgpu_device *adev,
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AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE);
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tiling_info->gfx9.shaderEnable = 1;
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#ifdef CONFIG_DRM_AMD_DC_DCN3_0
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if (adev->asic_type == CHIP_SIENNA_CICHLID)
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tiling_info->gfx9.num_pkrs = adev->gfx.config.gb_addr_config_fields.num_pkrs;
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#endif
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ret = fill_plane_dcc_attributes(adev, afb, format, rotation,
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plane_size, tiling_info,
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tiling_flags, dcc, address,
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@ -627,3 +627,23 @@ void dm_set_dcn_clocks(struct dc_context *ctx, struct dc_clocks *clks)
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{
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/* TODO: something */
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}
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#ifdef CONFIG_DRM_AMD_DC_DCN3_0
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void *dm_helpers_allocate_gpu_mem(
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struct dc_context *ctx,
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enum dc_gpu_mem_alloc_type type,
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size_t size,
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long long *addr)
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{
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// TODO
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return NULL;
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}
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void dm_helpers_free_gpu_mem(
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struct dc_context *ctx,
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enum dc_gpu_mem_alloc_type type,
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void *pvMem)
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{
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// TODO
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}
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#endif
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@ -390,6 +390,7 @@ union dc_tiling_info {
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bool meta_linear;
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bool rb_aligned;
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bool pipe_aligned;
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unsigned int num_pkrs;
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} gfx9;
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};
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@ -887,6 +887,15 @@ struct dsc_dec_dpcd_caps {
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uint32_t branch_max_line_width;
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};
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#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
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enum dc_gpu_mem_alloc_type {
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DC_MEM_ALLOC_TYPE_GART,
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DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
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DC_MEM_ALLOC_TYPE_INVISIBLE_FRAME_BUFFER,
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DC_MEM_ALLOC_TYPE_AGP
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};
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#endif
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enum dc_psr_version {
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DC_PSR_VERSION_1 = 0,
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DC_PSR_VERSION_UNSUPPORTED = 0xFFFFFFFF,
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@ -35,6 +35,29 @@
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struct dp_mst_stream_allocation_table;
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#ifdef CONFIG_DRM_AMD_DC_DCN3_0
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/*
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* Allocate memory accessible by the GPU
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*
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* frame buffer allocations must be aligned to a 4096-byte boundary
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*
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* Returns virtual address, sets addr to physical address
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*/
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void *dm_helpers_allocate_gpu_mem(
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struct dc_context *ctx,
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enum dc_gpu_mem_alloc_type type,
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size_t size,
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long long *addr);
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/*
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* Free the GPU-accessible memory at the virtual address pvMem
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*/
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void dm_helpers_free_gpu_mem(
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struct dc_context *ctx,
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enum dc_gpu_mem_alloc_type type,
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void *pvMem);
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#endif
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enum dc_edid_status dm_helpers_parse_edid_caps(
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struct dc_context *ctx,
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const struct dc_edid *edid,
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