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drm/tegra: dc: Record statistics
Record interrupt statistics, such as the number of frames and VBLANKs received and the number of FIFO underflow and overflows. Signed-off-by: Thierry Reding <treding@nvidia.com>
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parent
01a5da0c10
commit
791ddb1e1c
2 changed files with 49 additions and 3 deletions
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@ -76,6 +76,14 @@ to_tegra_plane_state(struct drm_plane_state *state)
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return NULL;
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}
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static void tegra_dc_stats_reset(struct tegra_dc_stats *stats)
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{
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stats->frames = 0;
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stats->vblank = 0;
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stats->underflow = 0;
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stats->overflow = 0;
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}
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/*
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* Reads the active copy of a register. This takes the dc->lock spinlock to
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* prevent races with the VBLANK processing which also needs access to the
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@ -1129,6 +1137,7 @@ static void tegra_crtc_disable(struct drm_crtc *crtc)
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tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
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}
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tegra_dc_stats_reset(&dc->stats);
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drm_crtc_vblank_off(crtc);
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}
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@ -1326,6 +1335,7 @@ static irqreturn_t tegra_dc_irq(int irq, void *data)
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/*
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dev_dbg(dc->dev, "%s(): frame end\n", __func__);
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*/
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dc->stats.frames++;
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}
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if (status & VBLANK_INT) {
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@ -1334,12 +1344,21 @@ static irqreturn_t tegra_dc_irq(int irq, void *data)
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*/
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drm_crtc_handle_vblank(&dc->base);
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tegra_dc_finish_page_flip(dc);
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dc->stats.vblank++;
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}
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if (status & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)) {
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/*
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dev_dbg(dc->dev, "%s(): underflow\n", __func__);
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*/
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dc->stats.underflow++;
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}
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if (status & (WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT)) {
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/*
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dev_dbg(dc->dev, "%s(): overflow\n", __func__);
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*/
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dc->stats.overflow++;
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}
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return IRQ_HANDLED;
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@ -1593,9 +1612,23 @@ static int tegra_dc_show_crc(struct seq_file *s, void *data)
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return 0;
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}
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static int tegra_dc_show_stats(struct seq_file *s, void *data)
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{
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struct drm_info_node *node = s->private;
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struct tegra_dc *dc = node->info_ent->data;
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seq_printf(s, "frames: %lu\n", dc->stats.frames);
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seq_printf(s, "vblank: %lu\n", dc->stats.vblank);
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seq_printf(s, "underflow: %lu\n", dc->stats.underflow);
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seq_printf(s, "overflow: %lu\n", dc->stats.overflow);
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return 0;
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}
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static struct drm_info_list debugfs_files[] = {
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{ "regs", tegra_dc_show_regs, 0, NULL },
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{ "crc", tegra_dc_show_crc, 0, NULL },
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{ "stats", tegra_dc_show_stats, 0, NULL },
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};
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static int tegra_dc_debugfs_init(struct tegra_dc *dc, struct drm_minor *minor)
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@ -1741,7 +1774,8 @@ static int tegra_dc_init(struct host1x_client *client)
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tegra_dc_writel(dc, value, DC_CMD_CONT_SYNCPT_VSYNC);
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}
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value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | WIN_A_OF_INT;
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value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
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WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
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tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);
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value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
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@ -1757,15 +1791,19 @@ static int tegra_dc_init(struct host1x_client *client)
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WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1);
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tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
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value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT;
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value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
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WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
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tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
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value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT;
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value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
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WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
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tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
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if (dc->soc->supports_border_color)
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tegra_dc_writel(dc, 0, DC_DISP_BORDER_COLOR);
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tegra_dc_stats_reset(&dc->stats);
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return 0;
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cleanup:
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@ -105,6 +105,13 @@ int tegra_drm_exit(struct tegra_drm *tegra);
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struct tegra_dc_soc_info;
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struct tegra_output;
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struct tegra_dc_stats {
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unsigned long frames;
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unsigned long vblank;
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unsigned long underflow;
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unsigned long overflow;
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};
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struct tegra_dc {
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struct host1x_client client;
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struct host1x_syncpt *syncpt;
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@ -122,6 +129,7 @@ struct tegra_dc {
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struct tegra_output *rgb;
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struct tegra_dc_stats stats;
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struct list_head list;
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struct drm_info_list *debugfs_files;
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