EDAC updates for 3.13
Highlights: * Support for Calxeda ECX-2000 memory controller, from Robert Richter * Misc Calxeda Highbank drivers and EDAC core cleanups, from Rob Herring and Robert Richter * New maintainer for Freescale's MPC85xx EDAC driver: Johannes Thumshirn -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.14 (GNU/Linux) iQIcBAABAgAGBQJSiRmeAAoJEBLB8Bhh3lVKYswQAKPCYSsIQg3L3K3320uvWV3x NEAxAAdYyN2ds7ksLv//54FBLgH9UeiC56glTMmnK9QvfGCcgHGo1WJCa84LwqIf M7H6mKSgTEBZXr7HpWgtarMYjpNve4Nh8SwHv7tlWRJNd3ufcBbOfCY6rEreULJd sBTRMuEPc1Ki7NxZr2m/xsPyzWXS1N1nSd2aewiszyY3Rwp1vIAPv/Chr7UwF/Fm GGeQonc801hVRIQONwxsXzS2qwj/wgx8OPab05psfMuv6CWLxQQJAzGWbe+gv3V4 mYx64+U4nOkQ/knRAf9s0fLwJX6DWSTtQer7m5YSUey0dYDfgV+DemLFvS5We7XB os9PBGL+0bGUrJ0cnLE6O+6S1qniWaKZrhSZndcYiVoQeDZmaMuartFlIaeRvY21 WJML2oqqUop2ZyaIKInJEyeD74FIf7BsG3V+RJwsCZx5+38Pm0EnBZqGJ9bnJl7x OxXlHjwjZRhlVFIdcN5WeaKoKmXpdcnzLcL1XE2wMgs9ZFaleeyTDXuQm+XxkKGd ExD/1TbAoBqFF7FwIAQwqPf1f2HPDBKlSg38X6l6NV5uLK/u5rdffKTMQPWi/6p2 RDO+Ddbypzm72850hcYc9mY+B8Qe3T3F/iKlbELiK1S5+IQzm/hmfTDcyKStwKZn cCTvsIo9QHflhshXR1a8 =pU/h -----END PGP SIGNATURE----- Merge tag 'edac_for_3.13' of git://git.kernel.org/pub/scm/linux/kernel/git/bp/bp Pull EDAC updates from Borislav Petkov: "Following up on last week's discussion, here's my part of the EDAC pile, highlights in the signed tag. The last two patches have a date from just now because I've just applied them to the tree after Johannes sent them to me earlier. I decided to forward them now because they're trivial. There's a third one for MPC85xx which adds PCIe error interrupt support but since it is not so trivial and hasn't seen any linux-next time, I'm deferring it to 3.14 EDAC update highlights: - Support for Calxeda ECX-2000 memory controller, from Robert Richter - Misc Calxeda Highbank drivers and EDAC core cleanups, from Rob Herring and Robert Richter - New maintainer for Freescale's MPC85xx EDAC driver: Johannes Thumshirn" * tag 'edac_for_3.13' of git://git.kernel.org/pub/scm/linux/kernel/git/bp/bp: edac/85xx: Remove mpc85xx_pci_err_remove EDAC: Add edac-mpc85xx driver to MAINTAINERS edac, highbank: Moving error injection to sysfs for edac edac, highbank: Add MAINTAINERS entry edac: Unify reporting of device info for device, mc and pci edac, highbank: Improve and unify naming edac, highbank: Add Calxeda ECX-2000 support ARM: dts: calxeda: move memory-controller node out of ecx-common.dtsi edac, highbank: Fix interrupt setup of mem and l2 controller
This commit is contained in:
commit
794e96e8ec
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@ -1,7 +1,9 @@
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Calxeda DDR memory controller
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Calxeda DDR memory controller
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Properties:
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Properties:
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- compatible : Should be "calxeda,hb-ddr-ctrl"
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- compatible : Should be:
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- "calxeda,hb-ddr-ctrl" for ECX-1000
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- "calxeda,ecx-2000-ddr-ctrl" for ECX-2000
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- reg : Address and size for DDR controller registers.
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- reg : Address and size for DDR controller registers.
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- interrupts : Interrupt for DDR controller.
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- interrupts : Interrupt for DDR controller.
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15
MAINTAINERS
15
MAINTAINERS
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@ -3063,6 +3063,14 @@ W: bluesmoke.sourceforge.net
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S: Maintained
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S: Maintained
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F: drivers/edac/amd64_edac*
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F: drivers/edac/amd64_edac*
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EDAC-CALXEDA
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M: Doug Thompson <dougthompson@xmission.com>
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M: Robert Richter <rric@kernel.org>
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L: linux-edac@vger.kernel.org
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W: bluesmoke.sourceforge.net
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S: Maintained
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F: drivers/edac/highbank*
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EDAC-CAVIUM
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EDAC-CAVIUM
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M: Ralf Baechle <ralf@linux-mips.org>
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M: Ralf Baechle <ralf@linux-mips.org>
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M: David Daney <david.daney@cavium.com>
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M: David Daney <david.daney@cavium.com>
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@ -3144,6 +3152,13 @@ W: bluesmoke.sourceforge.net
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S: Maintained
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S: Maintained
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F: drivers/edac/i82975x_edac.c
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F: drivers/edac/i82975x_edac.c
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EDAC-MPC85XX
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M: Johannes Thumshirn <johannes.thumshirn@men.de>
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L: linux-edac@vger.kernel.org
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W: bluesmoke.sourceforge.net
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S: Maintained
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F: drivers/edac/mpc85xx_edac.[ch]
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EDAC-PASEMI
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EDAC-PASEMI
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M: Egor Martovetsky <egor@pasemi.com>
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M: Egor Martovetsky <egor@pasemi.com>
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L: linux-edac@vger.kernel.org
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L: linux-edac@vger.kernel.org
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@ -85,6 +85,12 @@
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<1 10 0xf08>;
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<1 10 0xf08>;
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};
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};
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memory-controller@fff00000 {
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compatible = "calxeda,ecx-2000-ddr-ctrl";
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reg = <0xfff00000 0x1000>;
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interrupts = <0 91 4>;
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};
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intc: interrupt-controller@fff11000 {
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intc: interrupt-controller@fff11000 {
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compatible = "arm,cortex-a15-gic";
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compatible = "arm,cortex-a15-gic";
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#interrupt-cells = <3>;
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#interrupt-cells = <3>;
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@ -53,12 +53,6 @@
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status = "disabled";
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status = "disabled";
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};
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};
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memory-controller@fff00000 {
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compatible = "calxeda,hb-ddr-ctrl";
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reg = <0xfff00000 0x1000>;
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interrupts = <0 91 4>;
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};
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ipc@fff20000 {
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ipc@fff20000 {
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compatible = "arm,pl320", "arm,primecell";
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compatible = "arm,pl320", "arm,primecell";
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reg = <0xfff20000 0x1000>;
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reg = <0xfff20000 0x1000>;
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@ -86,6 +86,12 @@
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soc {
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soc {
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ranges = <0x00000000 0x00000000 0xffffffff>;
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ranges = <0x00000000 0x00000000 0xffffffff>;
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memory-controller@fff00000 {
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compatible = "calxeda,hb-ddr-ctrl";
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reg = <0xfff00000 0x1000>;
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interrupts = <0 91 4>;
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};
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timer@fff10600 {
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timer@fff10600 {
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compatible = "arm,cortex-a9-twd-timer";
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compatible = "arm,cortex-a9-twd-timer";
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reg = <0xfff10600 0x20>;
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reg = <0xfff10600 0x20>;
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@ -530,12 +530,9 @@ int edac_device_add_device(struct edac_device_ctl_info *edac_dev)
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/* Report action taken */
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/* Report action taken */
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edac_device_printk(edac_dev, KERN_INFO,
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edac_device_printk(edac_dev, KERN_INFO,
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"Giving out device to module '%s' controller "
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"Giving out device to module %s controller %s: DEV %s (%s)\n",
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"'%s': DEV '%s' (%s)\n",
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edac_dev->mod_name, edac_dev->ctl_name, edac_dev->dev_name,
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edac_dev->mod_name,
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edac_op_state_to_string(edac_dev->op_state));
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edac_dev->ctl_name,
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edac_dev_name(edac_dev),
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edac_op_state_to_string(edac_dev->op_state));
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mutex_unlock(&device_ctls_mutex);
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mutex_unlock(&device_ctls_mutex);
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return 0;
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return 0;
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@ -788,8 +788,10 @@ int edac_mc_add_mc(struct mem_ctl_info *mci)
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}
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}
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/* Report action taken */
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/* Report action taken */
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edac_mc_printk(mci, KERN_INFO, "Giving out device to '%s' '%s':"
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edac_mc_printk(mci, KERN_INFO,
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" DEV %s\n", mci->mod_name, mci->ctl_name, edac_dev_name(mci));
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"Giving out device to module %s controller %s: DEV %s (%s)\n",
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mci->mod_name, mci->ctl_name, mci->dev_name,
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edac_op_state_to_string(mci->op_state));
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edac_mc_owner = mci->mod_name;
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edac_mc_owner = mci->mod_name;
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@ -358,11 +358,9 @@ int edac_pci_add_device(struct edac_pci_ctl_info *pci, int edac_idx)
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}
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}
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edac_pci_printk(pci, KERN_INFO,
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edac_pci_printk(pci, KERN_INFO,
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"Giving out device to module '%s' controller '%s':"
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"Giving out device to module %s controller %s: DEV %s (%s)\n",
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" DEV '%s' (%s)\n",
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pci->mod_name, pci->ctl_name, pci->dev_name,
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pci->mod_name,
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edac_op_state_to_string(pci->op_state));
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pci->ctl_name,
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edac_dev_name(pci), edac_op_state_to_string(pci->op_state));
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mutex_unlock(&edac_pci_ctls_mutex);
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mutex_unlock(&edac_pci_ctls_mutex);
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return 0;
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return 0;
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@ -50,8 +50,15 @@ static irqreturn_t highbank_l2_err_handler(int irq, void *dev_id)
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return IRQ_HANDLED;
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return IRQ_HANDLED;
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}
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}
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static const struct of_device_id hb_l2_err_of_match[] = {
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{ .compatible = "calxeda,hb-sregs-l2-ecc", },
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{},
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};
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MODULE_DEVICE_TABLE(of, hb_l2_err_of_match);
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static int highbank_l2_err_probe(struct platform_device *pdev)
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static int highbank_l2_err_probe(struct platform_device *pdev)
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{
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{
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const struct of_device_id *id;
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struct edac_device_ctl_info *dci;
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struct edac_device_ctl_info *dci;
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struct hb_l2_drvdata *drvdata;
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struct hb_l2_drvdata *drvdata;
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struct resource *r;
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struct resource *r;
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@ -90,28 +97,32 @@ static int highbank_l2_err_probe(struct platform_device *pdev)
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goto err;
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goto err;
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}
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}
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id = of_match_device(hb_l2_err_of_match, &pdev->dev);
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dci->mod_name = pdev->dev.driver->name;
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dci->ctl_name = id ? id->compatible : "unknown";
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dci->dev_name = dev_name(&pdev->dev);
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if (edac_device_add_device(dci))
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goto err;
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drvdata->db_irq = platform_get_irq(pdev, 0);
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drvdata->db_irq = platform_get_irq(pdev, 0);
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res = devm_request_irq(&pdev->dev, drvdata->db_irq,
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res = devm_request_irq(&pdev->dev, drvdata->db_irq,
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highbank_l2_err_handler,
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highbank_l2_err_handler,
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0, dev_name(&pdev->dev), dci);
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0, dev_name(&pdev->dev), dci);
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if (res < 0)
|
if (res < 0)
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goto err;
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goto err2;
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drvdata->sb_irq = platform_get_irq(pdev, 1);
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drvdata->sb_irq = platform_get_irq(pdev, 1);
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res = devm_request_irq(&pdev->dev, drvdata->sb_irq,
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res = devm_request_irq(&pdev->dev, drvdata->sb_irq,
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highbank_l2_err_handler,
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highbank_l2_err_handler,
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0, dev_name(&pdev->dev), dci);
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0, dev_name(&pdev->dev), dci);
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if (res < 0)
|
if (res < 0)
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goto err;
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goto err2;
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dci->mod_name = dev_name(&pdev->dev);
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dci->dev_name = dev_name(&pdev->dev);
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if (edac_device_add_device(dci))
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goto err;
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devres_close_group(&pdev->dev, NULL);
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devres_close_group(&pdev->dev, NULL);
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return 0;
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return 0;
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err2:
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edac_device_del_device(&pdev->dev);
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err:
|
err:
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devres_release_group(&pdev->dev, NULL);
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devres_release_group(&pdev->dev, NULL);
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edac_device_free_ctl_info(dci);
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edac_device_free_ctl_info(dci);
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@ -127,12 +138,6 @@ static int highbank_l2_err_remove(struct platform_device *pdev)
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return 0;
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return 0;
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}
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}
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static const struct of_device_id hb_l2_err_of_match[] = {
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{ .compatible = "calxeda,hb-sregs-l2-ecc", },
|
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{},
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};
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MODULE_DEVICE_TABLE(of, hb_l2_err_of_match);
|
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||||||
|
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static struct platform_driver highbank_l2_edac_driver = {
|
static struct platform_driver highbank_l2_edac_driver = {
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.probe = highbank_l2_err_probe,
|
.probe = highbank_l2_err_probe,
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.remove = highbank_l2_err_remove,
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.remove = highbank_l2_err_remove,
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||||||
|
|
|
@ -26,31 +26,40 @@
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||||||
#include "edac_module.h"
|
#include "edac_module.h"
|
||||||
|
|
||||||
/* DDR Ctrlr Error Registers */
|
/* DDR Ctrlr Error Registers */
|
||||||
#define HB_DDR_ECC_OPT 0x128
|
|
||||||
#define HB_DDR_ECC_U_ERR_ADDR 0x130
|
#define HB_DDR_ECC_ERR_BASE 0x128
|
||||||
#define HB_DDR_ECC_U_ERR_STAT 0x134
|
#define MW_DDR_ECC_ERR_BASE 0x1b4
|
||||||
#define HB_DDR_ECC_U_ERR_DATAL 0x138
|
|
||||||
#define HB_DDR_ECC_U_ERR_DATAH 0x13c
|
#define HB_DDR_ECC_OPT 0x00
|
||||||
#define HB_DDR_ECC_C_ERR_ADDR 0x140
|
#define HB_DDR_ECC_U_ERR_ADDR 0x08
|
||||||
#define HB_DDR_ECC_C_ERR_STAT 0x144
|
#define HB_DDR_ECC_U_ERR_STAT 0x0c
|
||||||
#define HB_DDR_ECC_C_ERR_DATAL 0x148
|
#define HB_DDR_ECC_U_ERR_DATAL 0x10
|
||||||
#define HB_DDR_ECC_C_ERR_DATAH 0x14c
|
#define HB_DDR_ECC_U_ERR_DATAH 0x14
|
||||||
#define HB_DDR_ECC_INT_STATUS 0x180
|
#define HB_DDR_ECC_C_ERR_ADDR 0x18
|
||||||
#define HB_DDR_ECC_INT_ACK 0x184
|
#define HB_DDR_ECC_C_ERR_STAT 0x1c
|
||||||
#define HB_DDR_ECC_U_ERR_ID 0x424
|
#define HB_DDR_ECC_C_ERR_DATAL 0x20
|
||||||
#define HB_DDR_ECC_C_ERR_ID 0x428
|
#define HB_DDR_ECC_C_ERR_DATAH 0x24
|
||||||
|
|
||||||
|
#define HB_DDR_ECC_OPT_MODE_MASK 0x3
|
||||||
|
#define HB_DDR_ECC_OPT_FWC 0x100
|
||||||
|
#define HB_DDR_ECC_OPT_XOR_SHIFT 16
|
||||||
|
|
||||||
|
/* DDR Ctrlr Interrupt Registers */
|
||||||
|
|
||||||
|
#define HB_DDR_ECC_INT_BASE 0x180
|
||||||
|
#define MW_DDR_ECC_INT_BASE 0x218
|
||||||
|
|
||||||
|
#define HB_DDR_ECC_INT_STATUS 0x00
|
||||||
|
#define HB_DDR_ECC_INT_ACK 0x04
|
||||||
|
|
||||||
#define HB_DDR_ECC_INT_STAT_CE 0x8
|
#define HB_DDR_ECC_INT_STAT_CE 0x8
|
||||||
#define HB_DDR_ECC_INT_STAT_DOUBLE_CE 0x10
|
#define HB_DDR_ECC_INT_STAT_DOUBLE_CE 0x10
|
||||||
#define HB_DDR_ECC_INT_STAT_UE 0x20
|
#define HB_DDR_ECC_INT_STAT_UE 0x20
|
||||||
#define HB_DDR_ECC_INT_STAT_DOUBLE_UE 0x40
|
#define HB_DDR_ECC_INT_STAT_DOUBLE_UE 0x40
|
||||||
|
|
||||||
#define HB_DDR_ECC_OPT_MODE_MASK 0x3
|
|
||||||
#define HB_DDR_ECC_OPT_FWC 0x100
|
|
||||||
#define HB_DDR_ECC_OPT_XOR_SHIFT 16
|
|
||||||
|
|
||||||
struct hb_mc_drvdata {
|
struct hb_mc_drvdata {
|
||||||
void __iomem *mc_vbase;
|
void __iomem *mc_err_base;
|
||||||
|
void __iomem *mc_int_base;
|
||||||
};
|
};
|
||||||
|
|
||||||
static irqreturn_t highbank_mc_err_handler(int irq, void *dev_id)
|
static irqreturn_t highbank_mc_err_handler(int irq, void *dev_id)
|
||||||
|
@ -60,10 +69,10 @@ static irqreturn_t highbank_mc_err_handler(int irq, void *dev_id)
|
||||||
u32 status, err_addr;
|
u32 status, err_addr;
|
||||||
|
|
||||||
/* Read the interrupt status register */
|
/* Read the interrupt status register */
|
||||||
status = readl(drvdata->mc_vbase + HB_DDR_ECC_INT_STATUS);
|
status = readl(drvdata->mc_int_base + HB_DDR_ECC_INT_STATUS);
|
||||||
|
|
||||||
if (status & HB_DDR_ECC_INT_STAT_UE) {
|
if (status & HB_DDR_ECC_INT_STAT_UE) {
|
||||||
err_addr = readl(drvdata->mc_vbase + HB_DDR_ECC_U_ERR_ADDR);
|
err_addr = readl(drvdata->mc_err_base + HB_DDR_ECC_U_ERR_ADDR);
|
||||||
edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
|
edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
|
||||||
err_addr >> PAGE_SHIFT,
|
err_addr >> PAGE_SHIFT,
|
||||||
err_addr & ~PAGE_MASK, 0,
|
err_addr & ~PAGE_MASK, 0,
|
||||||
|
@ -71,9 +80,9 @@ static irqreturn_t highbank_mc_err_handler(int irq, void *dev_id)
|
||||||
mci->ctl_name, "");
|
mci->ctl_name, "");
|
||||||
}
|
}
|
||||||
if (status & HB_DDR_ECC_INT_STAT_CE) {
|
if (status & HB_DDR_ECC_INT_STAT_CE) {
|
||||||
u32 syndrome = readl(drvdata->mc_vbase + HB_DDR_ECC_C_ERR_STAT);
|
u32 syndrome = readl(drvdata->mc_err_base + HB_DDR_ECC_C_ERR_STAT);
|
||||||
syndrome = (syndrome >> 8) & 0xff;
|
syndrome = (syndrome >> 8) & 0xff;
|
||||||
err_addr = readl(drvdata->mc_vbase + HB_DDR_ECC_C_ERR_ADDR);
|
err_addr = readl(drvdata->mc_err_base + HB_DDR_ECC_C_ERR_ADDR);
|
||||||
edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
|
edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
|
||||||
err_addr >> PAGE_SHIFT,
|
err_addr >> PAGE_SHIFT,
|
||||||
err_addr & ~PAGE_MASK, syndrome,
|
err_addr & ~PAGE_MASK, syndrome,
|
||||||
|
@ -82,66 +91,79 @@ static irqreturn_t highbank_mc_err_handler(int irq, void *dev_id)
|
||||||
}
|
}
|
||||||
|
|
||||||
/* clear the error, clears the interrupt */
|
/* clear the error, clears the interrupt */
|
||||||
writel(status, drvdata->mc_vbase + HB_DDR_ECC_INT_ACK);
|
writel(status, drvdata->mc_int_base + HB_DDR_ECC_INT_ACK);
|
||||||
return IRQ_HANDLED;
|
return IRQ_HANDLED;
|
||||||
}
|
}
|
||||||
|
|
||||||
#ifdef CONFIG_EDAC_DEBUG
|
static void highbank_mc_err_inject(struct mem_ctl_info *mci, u8 synd)
|
||||||
static ssize_t highbank_mc_err_inject_write(struct file *file,
|
|
||||||
const char __user *data,
|
|
||||||
size_t count, loff_t *ppos)
|
|
||||||
{
|
{
|
||||||
struct mem_ctl_info *mci = file->private_data;
|
|
||||||
struct hb_mc_drvdata *pdata = mci->pvt_info;
|
struct hb_mc_drvdata *pdata = mci->pvt_info;
|
||||||
char buf[32];
|
|
||||||
size_t buf_size;
|
|
||||||
u32 reg;
|
u32 reg;
|
||||||
|
|
||||||
|
reg = readl(pdata->mc_err_base + HB_DDR_ECC_OPT);
|
||||||
|
reg &= HB_DDR_ECC_OPT_MODE_MASK;
|
||||||
|
reg |= (synd << HB_DDR_ECC_OPT_XOR_SHIFT) | HB_DDR_ECC_OPT_FWC;
|
||||||
|
writel(reg, pdata->mc_err_base + HB_DDR_ECC_OPT);
|
||||||
|
}
|
||||||
|
|
||||||
|
#define to_mci(k) container_of(k, struct mem_ctl_info, dev)
|
||||||
|
|
||||||
|
static ssize_t highbank_mc_inject_ctrl(struct device *dev,
|
||||||
|
struct device_attribute *attr, const char *buf, size_t count)
|
||||||
|
{
|
||||||
|
struct mem_ctl_info *mci = to_mci(dev);
|
||||||
u8 synd;
|
u8 synd;
|
||||||
|
|
||||||
buf_size = min(count, (sizeof(buf)-1));
|
if (kstrtou8(buf, 16, &synd))
|
||||||
if (copy_from_user(buf, data, buf_size))
|
return -EINVAL;
|
||||||
return -EFAULT;
|
|
||||||
buf[buf_size] = 0;
|
|
||||||
|
|
||||||
if (!kstrtou8(buf, 16, &synd)) {
|
highbank_mc_err_inject(mci, synd);
|
||||||
reg = readl(pdata->mc_vbase + HB_DDR_ECC_OPT);
|
|
||||||
reg &= HB_DDR_ECC_OPT_MODE_MASK;
|
|
||||||
reg |= (synd << HB_DDR_ECC_OPT_XOR_SHIFT) | HB_DDR_ECC_OPT_FWC;
|
|
||||||
writel(reg, pdata->mc_vbase + HB_DDR_ECC_OPT);
|
|
||||||
}
|
|
||||||
|
|
||||||
return count;
|
return count;
|
||||||
}
|
}
|
||||||
|
|
||||||
static const struct file_operations highbank_mc_debug_inject_fops = {
|
static DEVICE_ATTR(inject_ctrl, S_IWUSR, NULL, highbank_mc_inject_ctrl);
|
||||||
.open = simple_open,
|
|
||||||
.write = highbank_mc_err_inject_write,
|
struct hb_mc_settings {
|
||||||
.llseek = generic_file_llseek,
|
int err_offset;
|
||||||
|
int int_offset;
|
||||||
};
|
};
|
||||||
|
|
||||||
static void highbank_mc_create_debugfs_nodes(struct mem_ctl_info *mci)
|
static struct hb_mc_settings hb_settings = {
|
||||||
{
|
.err_offset = HB_DDR_ECC_ERR_BASE,
|
||||||
if (mci->debugfs)
|
.int_offset = HB_DDR_ECC_INT_BASE,
|
||||||
debugfs_create_file("inject_ctrl", S_IWUSR, mci->debugfs, mci,
|
};
|
||||||
&highbank_mc_debug_inject_fops);
|
|
||||||
;
|
static struct hb_mc_settings mw_settings = {
|
||||||
}
|
.err_offset = MW_DDR_ECC_ERR_BASE,
|
||||||
#else
|
.int_offset = MW_DDR_ECC_INT_BASE,
|
||||||
static void highbank_mc_create_debugfs_nodes(struct mem_ctl_info *mci)
|
};
|
||||||
{}
|
|
||||||
#endif
|
static struct of_device_id hb_ddr_ctrl_of_match[] = {
|
||||||
|
{ .compatible = "calxeda,hb-ddr-ctrl", .data = &hb_settings },
|
||||||
|
{ .compatible = "calxeda,ecx-2000-ddr-ctrl", .data = &mw_settings },
|
||||||
|
{},
|
||||||
|
};
|
||||||
|
MODULE_DEVICE_TABLE(of, hb_ddr_ctrl_of_match);
|
||||||
|
|
||||||
static int highbank_mc_probe(struct platform_device *pdev)
|
static int highbank_mc_probe(struct platform_device *pdev)
|
||||||
{
|
{
|
||||||
|
const struct of_device_id *id;
|
||||||
|
const struct hb_mc_settings *settings;
|
||||||
struct edac_mc_layer layers[2];
|
struct edac_mc_layer layers[2];
|
||||||
struct mem_ctl_info *mci;
|
struct mem_ctl_info *mci;
|
||||||
struct hb_mc_drvdata *drvdata;
|
struct hb_mc_drvdata *drvdata;
|
||||||
struct dimm_info *dimm;
|
struct dimm_info *dimm;
|
||||||
struct resource *r;
|
struct resource *r;
|
||||||
|
void __iomem *base;
|
||||||
u32 control;
|
u32 control;
|
||||||
int irq;
|
int irq;
|
||||||
int res = 0;
|
int res = 0;
|
||||||
|
|
||||||
|
id = of_match_device(hb_ddr_ctrl_of_match, &pdev->dev);
|
||||||
|
if (!id)
|
||||||
|
return -ENODEV;
|
||||||
|
|
||||||
layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
|
layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
|
||||||
layers[0].size = 1;
|
layers[0].size = 1;
|
||||||
layers[0].is_virt_csrow = true;
|
layers[0].is_virt_csrow = true;
|
||||||
|
@ -174,35 +196,31 @@ static int highbank_mc_probe(struct platform_device *pdev)
|
||||||
goto err;
|
goto err;
|
||||||
}
|
}
|
||||||
|
|
||||||
drvdata->mc_vbase = devm_ioremap(&pdev->dev,
|
base = devm_ioremap(&pdev->dev, r->start, resource_size(r));
|
||||||
r->start, resource_size(r));
|
if (!base) {
|
||||||
if (!drvdata->mc_vbase) {
|
|
||||||
dev_err(&pdev->dev, "Unable to map regs\n");
|
dev_err(&pdev->dev, "Unable to map regs\n");
|
||||||
res = -ENOMEM;
|
res = -ENOMEM;
|
||||||
goto err;
|
goto err;
|
||||||
}
|
}
|
||||||
|
|
||||||
control = readl(drvdata->mc_vbase + HB_DDR_ECC_OPT) & 0x3;
|
settings = id->data;
|
||||||
|
drvdata->mc_err_base = base + settings->err_offset;
|
||||||
|
drvdata->mc_int_base = base + settings->int_offset;
|
||||||
|
|
||||||
|
control = readl(drvdata->mc_err_base + HB_DDR_ECC_OPT) & 0x3;
|
||||||
if (!control || (control == 0x2)) {
|
if (!control || (control == 0x2)) {
|
||||||
dev_err(&pdev->dev, "No ECC present, or ECC disabled\n");
|
dev_err(&pdev->dev, "No ECC present, or ECC disabled\n");
|
||||||
res = -ENODEV;
|
res = -ENODEV;
|
||||||
goto err;
|
goto err;
|
||||||
}
|
}
|
||||||
|
|
||||||
irq = platform_get_irq(pdev, 0);
|
|
||||||
res = devm_request_irq(&pdev->dev, irq, highbank_mc_err_handler,
|
|
||||||
0, dev_name(&pdev->dev), mci);
|
|
||||||
if (res < 0) {
|
|
||||||
dev_err(&pdev->dev, "Unable to request irq %d\n", irq);
|
|
||||||
goto err;
|
|
||||||
}
|
|
||||||
|
|
||||||
mci->mtype_cap = MEM_FLAG_DDR3;
|
mci->mtype_cap = MEM_FLAG_DDR3;
|
||||||
mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
|
mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
|
||||||
mci->edac_cap = EDAC_FLAG_SECDED;
|
mci->edac_cap = EDAC_FLAG_SECDED;
|
||||||
mci->mod_name = dev_name(&pdev->dev);
|
mci->mod_name = pdev->dev.driver->name;
|
||||||
mci->mod_ver = "1";
|
mci->mod_ver = "1";
|
||||||
mci->ctl_name = dev_name(&pdev->dev);
|
mci->ctl_name = id->compatible;
|
||||||
|
mci->dev_name = dev_name(&pdev->dev);
|
||||||
mci->scrub_mode = SCRUB_SW_SRC;
|
mci->scrub_mode = SCRUB_SW_SRC;
|
||||||
|
|
||||||
/* Only a single 4GB DIMM is supported */
|
/* Only a single 4GB DIMM is supported */
|
||||||
|
@ -217,10 +235,20 @@ static int highbank_mc_probe(struct platform_device *pdev)
|
||||||
if (res < 0)
|
if (res < 0)
|
||||||
goto err;
|
goto err;
|
||||||
|
|
||||||
highbank_mc_create_debugfs_nodes(mci);
|
irq = platform_get_irq(pdev, 0);
|
||||||
|
res = devm_request_irq(&pdev->dev, irq, highbank_mc_err_handler,
|
||||||
|
0, dev_name(&pdev->dev), mci);
|
||||||
|
if (res < 0) {
|
||||||
|
dev_err(&pdev->dev, "Unable to request irq %d\n", irq);
|
||||||
|
goto err2;
|
||||||
|
}
|
||||||
|
|
||||||
|
device_create_file(&mci->dev, &dev_attr_inject_ctrl);
|
||||||
|
|
||||||
devres_close_group(&pdev->dev, NULL);
|
devres_close_group(&pdev->dev, NULL);
|
||||||
return 0;
|
return 0;
|
||||||
|
err2:
|
||||||
|
edac_mc_del_mc(&pdev->dev);
|
||||||
err:
|
err:
|
||||||
devres_release_group(&pdev->dev, NULL);
|
devres_release_group(&pdev->dev, NULL);
|
||||||
edac_mc_free(mci);
|
edac_mc_free(mci);
|
||||||
|
@ -231,17 +259,12 @@ static int highbank_mc_remove(struct platform_device *pdev)
|
||||||
{
|
{
|
||||||
struct mem_ctl_info *mci = platform_get_drvdata(pdev);
|
struct mem_ctl_info *mci = platform_get_drvdata(pdev);
|
||||||
|
|
||||||
|
device_remove_file(&mci->dev, &dev_attr_inject_ctrl);
|
||||||
edac_mc_del_mc(&pdev->dev);
|
edac_mc_del_mc(&pdev->dev);
|
||||||
edac_mc_free(mci);
|
edac_mc_free(mci);
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
static const struct of_device_id hb_ddr_ctrl_of_match[] = {
|
|
||||||
{ .compatible = "calxeda,hb-ddr-ctrl", },
|
|
||||||
{},
|
|
||||||
};
|
|
||||||
MODULE_DEVICE_TABLE(of, hb_ddr_ctrl_of_match);
|
|
||||||
|
|
||||||
static struct platform_driver highbank_mc_edac_driver = {
|
static struct platform_driver highbank_mc_edac_driver = {
|
||||||
.probe = highbank_mc_probe,
|
.probe = highbank_mc_probe,
|
||||||
.remove = highbank_mc_remove,
|
.remove = highbank_mc_remove,
|
||||||
|
|
|
@ -327,28 +327,6 @@ err:
|
||||||
}
|
}
|
||||||
EXPORT_SYMBOL(mpc85xx_pci_err_probe);
|
EXPORT_SYMBOL(mpc85xx_pci_err_probe);
|
||||||
|
|
||||||
static int mpc85xx_pci_err_remove(struct platform_device *op)
|
|
||||||
{
|
|
||||||
struct edac_pci_ctl_info *pci = dev_get_drvdata(&op->dev);
|
|
||||||
struct mpc85xx_pci_pdata *pdata = pci->pvt_info;
|
|
||||||
|
|
||||||
edac_dbg(0, "\n");
|
|
||||||
|
|
||||||
out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_CAP_DR,
|
|
||||||
orig_pci_err_cap_dr);
|
|
||||||
|
|
||||||
out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN, orig_pci_err_en);
|
|
||||||
|
|
||||||
edac_pci_del_device(pci->dev);
|
|
||||||
|
|
||||||
if (edac_op_state == EDAC_OPSTATE_INT)
|
|
||||||
irq_dispose_mapping(pdata->irq);
|
|
||||||
|
|
||||||
edac_pci_free_ctl_info(pci);
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
#endif /* CONFIG_PCI */
|
#endif /* CONFIG_PCI */
|
||||||
|
|
||||||
/**************************** L2 Err device ***************************/
|
/**************************** L2 Err device ***************************/
|
||||||
|
|
Loading…
Reference in New Issue