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mtd: nand: denali: fix setup_data_interface to meet tCCS delay
The WE_2_RE register specifies the number of clock cycles inserted between the rising edge of #WE and the falling edge of #RE. The current setup_data_interface implementation takes care of tWHR, but tCCS is missing. Wait for max(tCSS, tWHR) to meet the spec. With setup_data_interface() properly programmed, the Denali NAND controller can observe the timing, so NAND_WAIT_TCCS flag is unneeded. Clarify this in the comment block. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
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1 changed files with 8 additions and 2 deletions
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@ -1004,8 +1004,14 @@ static int denali_setup_data_interface(struct mtd_info *mtd, int chipnr,
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tmp |= FIELD_PREP(RE_2_RE__VALUE, re_2_re);
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iowrite32(tmp, denali->reg + RE_2_RE);
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/* tWHR -> WE_2_RE */
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we_2_re = DIV_ROUND_UP(timings->tWHR_min, t_clk);
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/*
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* tCCS, tWHR -> WE_2_RE
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*
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* With WE_2_RE properly set, the Denali controller automatically takes
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* care of the delay; the driver need not set NAND_WAIT_TCCS.
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*/
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we_2_re = DIV_ROUND_UP(max(timings->tCCS_min, timings->tWHR_min),
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t_clk);
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we_2_re = min_t(int, we_2_re, TWHR2_AND_WE_2_RE__WE_2_RE);
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tmp = ioread32(denali->reg + TWHR2_AND_WE_2_RE);
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