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watchdog: s3c2410_wdt: Add support for Google gs101 SoC

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This patch adds the compatibles and drvdata for the Google
gs101 SoC found in Pixel 6, Pixel 6a & Pixel 6 pro phones.

Similar to Exynos850 it has two watchdog instances, one for
each cluster and has some control bits in PMU registers.

gs101 also has the dbgack_mask bit in wtcon register, so
we also enable QUIRK_HAS_DBGACK_BIT.

Tested-by: Will McVicker <willmcvicker@google.com>
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Link: https://lore.kernel.org/r/20231211162331.435900-13-peter.griffin@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
This commit is contained in:
Peter Griffin 2023-12-11 16:23:27 +00:00 committed by Krzysztof Kozlowski
parent d429928dde
commit 796bb2d3a1
1 changed files with 43 additions and 4 deletions
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47
drivers/watchdog/s3c2410_wdt.c
View file

@ -69,6 +69,13 @@
#define EXYNOSAUTOV9_CLUSTER0_WDTRESET_BIT 25
#define EXYNOSAUTOV9_CLUSTER1_WDTRESET_BIT 24
#define GS_CLUSTER0_NONCPU_OUT 0x1220
#define GS_CLUSTER1_NONCPU_OUT 0x1420
#define GS_CLUSTER0_NONCPU_INT_EN 0x1244
#define GS_CLUSTER1_NONCPU_INT_EN 0x1444
#define GS_CLUSTER2_NONCPU_INT_EN 0x1644
#define GS_RST_STAT_REG_OFFSET 0x3B44
/**
* DOC: Quirk flags for different Samsung watchdog IP-cores
*
@ -270,7 +277,35 @@ static const struct s3c2410_wdt_variant drv_data_exynosautov9_cl1 = {
QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_CNT_EN,
};
static const struct s3c2410_wdt_variant drv_data_gs101_cl0 = {
.mask_reset_reg = GS_CLUSTER0_NONCPU_INT_EN,
.mask_bit = 2,
.mask_reset_inv = true,
.rst_stat_reg = GS_RST_STAT_REG_OFFSET,
.rst_stat_bit = 0,
.cnt_en_reg = GS_CLUSTER0_NONCPU_OUT,
.cnt_en_bit = 8,
.quirks = QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_MASK_RESET |
QUIRK_HAS_PMU_CNT_EN | QUIRK_HAS_WTCLRINT_REG |
QUIRK_HAS_DBGACK_BIT,
};
static const struct s3c2410_wdt_variant drv_data_gs101_cl1 = {
.mask_reset_reg = GS_CLUSTER1_NONCPU_INT_EN,
.mask_bit = 2,
.mask_reset_inv = true,
.rst_stat_reg = GS_RST_STAT_REG_OFFSET,
.rst_stat_bit = 1,
.cnt_en_reg = GS_CLUSTER1_NONCPU_OUT,
.cnt_en_bit = 7,
.quirks = QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_MASK_RESET |
QUIRK_HAS_PMU_CNT_EN | QUIRK_HAS_WTCLRINT_REG |
QUIRK_HAS_DBGACK_BIT,
};
static const struct of_device_id s3c2410_wdt_match[] = {
{ .compatible = "google,gs101-wdt",
.data = &drv_data_gs101_cl0 },
{ .compatible = "samsung,s3c2410-wdt",
.data = &drv_data_s3c2410 },
{ .compatible = "samsung,s3c6410-wdt",
@ -607,7 +642,8 @@ s3c2410_get_wdt_drv_data(struct platform_device *pdev, struct s3c2410_wdt *wdt)
#ifdef CONFIG_OF
/* Choose Exynos850/ExynosAutov9 driver data w.r.t. cluster index */
if (variant == &drv_data_exynos850_cl0 ||
variant == &drv_data_exynosautov9_cl0) {
variant == &drv_data_exynosautov9_cl0 ||
variant == &drv_data_gs101_cl0) {
u32 index;
int err;
@ -620,9 +656,12 @@ s3c2410_get_wdt_drv_data(struct platform_device *pdev, struct s3c2410_wdt *wdt)
case 0:
break;
case 1:
variant = (variant == &drv_data_exynos850_cl0) ?
&drv_data_exynos850_cl1 :
&drv_data_exynosautov9_cl1;
if (variant == &drv_data_exynos850_cl0)
variant = &drv_data_exynos850_cl1;
else if (variant == &drv_data_exynosautov9_cl0)
variant = &drv_data_exynosautov9_cl1;
else if (variant == &drv_data_gs101_cl0)
variant = &drv_data_gs101_cl1;
break;
default:
return dev_err_probe(dev, -EINVAL, "wrong cluster index: %u\n", index);