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spi: davinci: enable both activation and deactivation of chip-selects
Let davinci_spi_chipselect() perform both activation and deactivation of chip selects. This lets spi_bitbang fully control chip select activation, as intended by the SPI API. With this change, the chip select activation code need not be duplicated in davinci_spi_bufs_{pio|dma}(). Also, keeping chip select active control is removed as a platform data and simply controlled using information from spi_bitbang on whether chip slect should be activated or de-activated. Signed-off-by: Brian Niebuhr <bniebuhr@efjohnson.com> Tested-By: Michael Williamson <michael.williamson@criticallink.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com>
This commit is contained in:
parent
843a713bc5
commit
7978b8c385
4 changed files with 18 additions and 38 deletions
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@ -413,7 +413,6 @@ static struct davinci_spi_platform_data dm355_spi0_pdata = {
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.version = SPI_VERSION_1,
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.num_chipselect = 2,
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.clk_internal = 1,
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.cs_hold = 1,
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.intr_level = 0,
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.poll_mode = 1, /* 0 -> interrupt mode 1-> polling mode */
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.c2tdelay = 0,
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@ -626,7 +626,6 @@ static struct davinci_spi_platform_data dm365_spi0_pdata = {
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.version = SPI_VERSION_1,
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.num_chipselect = 2,
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.clk_internal = 1,
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.cs_hold = 1,
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.intr_level = 0,
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.poll_mode = 1, /* 0 -> interrupt mode 1-> polling mode */
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.c2tdelay = 0,
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@ -33,7 +33,6 @@ struct davinci_spi_platform_data {
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u8 wait_enable;
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u8 timer_disable;
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u8 clk_internal;
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u8 cs_hold;
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u8 intr_level;
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u8 poll_mode;
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u8 use_dma;
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@ -66,7 +66,7 @@
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#define SPI_INTLVL_0 0x00000000u
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/* SPIDAT1 */
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#define SPIDAT1_CSHOLD_SHIFT 28
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#define SPIDAT1_CSHOLD_MASK BIT(28)
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#define SPIDAT1_CSNR_SHIFT 16
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#define SPIGCR1_CLKMOD_MASK BIT(1)
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#define SPIGCR1_MASTER_MASK BIT(0)
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@ -235,7 +235,8 @@ static void davinci_spi_chipselect(struct spi_device *spi, int value)
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{
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struct davinci_spi *davinci_spi;
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struct davinci_spi_platform_data *pdata;
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u32 data1_reg_val = 0;
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u32 data1_reg_val;
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u8 chip_sel = spi->chip_select;
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davinci_spi = spi_master_get_devdata(spi->master);
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pdata = davinci_spi->pdata;
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@ -244,14 +245,17 @@ static void davinci_spi_chipselect(struct spi_device *spi, int value)
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* Board specific chip select logic decides the polarity and cs
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* line for the controller
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*/
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if (value == BITBANG_CS_INACTIVE) {
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data1_reg_val |= CS_DEFAULT << SPIDAT1_CSNR_SHIFT;
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iowrite32(data1_reg_val, davinci_spi->base + SPIDAT1);
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while ((ioread32(davinci_spi->base + SPIBUF)
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& SPIBUF_RXEMPTY_MASK) == 0)
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cpu_relax();
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data1_reg_val = CS_DEFAULT << SPIDAT1_CSNR_SHIFT;
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if (value == BITBANG_CS_ACTIVE) {
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data1_reg_val |= SPIDAT1_CSHOLD_MASK;
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data1_reg_val &= ~((0x1 << chip_sel) << SPIDAT1_CSNR_SHIFT);
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}
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iowrite32(data1_reg_val, davinci_spi->base + SPIDAT1);
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while ((ioread32(davinci_spi->base + SPIBUF)
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& SPIBUF_RXEMPTY_MASK) == 0)
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cpu_relax();
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}
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/**
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@ -632,7 +636,7 @@ static int davinci_spi_bufs_pio(struct spi_device *spi, struct spi_transfer *t)
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{
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struct davinci_spi *davinci_spi;
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int int_status, count, ret;
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u8 conv, tmp;
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u8 conv;
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u32 tx_data, data1_reg_val;
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u32 buf_val, flg_val;
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struct davinci_spi_platform_data *pdata;
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@ -647,6 +651,8 @@ static int davinci_spi_bufs_pio(struct spi_device *spi, struct spi_transfer *t)
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conv = davinci_spi->slave[spi->chip_select].bytes_per_word;
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davinci_spi->count = t->len / conv;
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data1_reg_val = ioread32(davinci_spi->base + SPIDAT1);
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INIT_COMPLETION(davinci_spi->done);
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ret = davinci_spi_bufs_prep(spi, davinci_spi);
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@ -661,16 +667,6 @@ static int davinci_spi_bufs_pio(struct spi_device *spi, struct spi_transfer *t)
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davinci_spi->base + SPIDELAY);
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count = davinci_spi->count;
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data1_reg_val = pdata->cs_hold << SPIDAT1_CSHOLD_SHIFT;
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tmp = ~(0x1 << spi->chip_select);
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clear_io_bits(davinci_spi->base + SPIDEF, ~tmp);
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data1_reg_val |= tmp << SPIDAT1_CSNR_SHIFT;
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while ((ioread32(davinci_spi->base + SPIBUF)
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& SPIBUF_RXEMPTY_MASK) == 0)
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cpu_relax();
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/* Determine the command to execute READ or WRITE */
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if (t->tx_buf) {
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@ -770,7 +766,6 @@ static int davinci_spi_bufs_dma(struct spi_device *spi, struct spi_transfer *t)
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int int_status = 0;
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int count, temp_count;
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u8 conv = 1;
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u8 tmp;
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u32 data1_reg_val;
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struct davinci_spi_dma *davinci_spi_dma;
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int word_len, data_type, ret;
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@ -794,6 +789,8 @@ static int davinci_spi_bufs_dma(struct spi_device *spi, struct spi_transfer *t)
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conv = davinci_spi->slave[spi->chip_select].bytes_per_word;
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davinci_spi->count = t->len / conv;
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data1_reg_val = ioread32(davinci_spi->base + SPIDAT1);
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INIT_COMPLETION(davinci_spi->done);
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init_completion(&davinci_spi_dma->dma_rx_completion);
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@ -820,28 +817,14 @@ static int davinci_spi_bufs_dma(struct spi_device *spi, struct spi_transfer *t)
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davinci_spi->base + SPIDELAY);
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count = davinci_spi->count; /* the number of elements */
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data1_reg_val = pdata->cs_hold << SPIDAT1_CSHOLD_SHIFT;
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/* CS default = 0xFF */
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tmp = ~(0x1 << spi->chip_select);
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clear_io_bits(davinci_spi->base + SPIDEF, ~tmp);
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data1_reg_val |= tmp << SPIDAT1_CSNR_SHIFT;
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/* disable all interrupts for dma transfers */
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clear_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKALL);
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/* Disable SPI to write configuration bits in SPIDAT */
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clear_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);
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iowrite32(data1_reg_val, davinci_spi->base + SPIDAT1);
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/* Enable SPI */
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set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);
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while ((ioread32(davinci_spi->base + SPIBUF)
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& SPIBUF_RXEMPTY_MASK) == 0)
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cpu_relax();
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if (t->tx_buf) {
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t->tx_dma = dma_map_single(&spi->dev, (void *)t->tx_buf, count,
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DMA_TO_DEVICE);
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