mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-09-06 10:57:46 +00:00
Merge branch 'gic/cleanup' into next/soc2
Both zynq and shmobile have conflicts against the gic cleanup series, resolved here. Conflicts: arch/arm/mach-shmobile/smp-emev2.c arch/arm/mach-shmobile/smp-r8a7779.c arch/arm/mach-shmobile/smp-sh73a0.c arch/arm/mach-zynq/platsmp.c drivers/gpio/gpio-pl061.c Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
commit
797b3a9ee7
40 changed files with 100 additions and 210 deletions
|
@ -30,6 +30,11 @@ extern void asm_do_IRQ(unsigned int, struct pt_regs *);
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void handle_IRQ(unsigned int, struct pt_regs *);
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void init_IRQ(void);
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#ifdef CONFIG_MULTI_IRQ_HANDLER
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extern void (*handle_arch_irq)(struct pt_regs *);
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extern void set_handle_irq(void (*handle_irq)(struct pt_regs *));
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#endif
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#endif
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#endif
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@ -20,11 +20,6 @@ struct seq_file;
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extern void init_FIQ(int);
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extern int show_fiq_list(struct seq_file *, int);
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#ifdef CONFIG_MULTI_IRQ_HANDLER
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extern void (*handle_arch_irq)(struct pt_regs *);
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extern void set_handle_irq(void (*handle_irq)(struct pt_regs *));
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#endif
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/*
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* This is for easy migration, but should be changed in the source
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*/
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@ -35,35 +30,4 @@ do { \
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raw_spin_unlock(&desc->lock); \
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} while(0)
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#ifndef __ASSEMBLY__
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/*
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* Entry/exit functions for chained handlers where the primary IRQ chip
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* may implement either fasteoi or level-trigger flow control.
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*/
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static inline void chained_irq_enter(struct irq_chip *chip,
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struct irq_desc *desc)
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{
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/* FastEOI controllers require no action on entry. */
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if (chip->irq_eoi)
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return;
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if (chip->irq_mask_ack) {
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chip->irq_mask_ack(&desc->irq_data);
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} else {
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chip->irq_mask(&desc->irq_data);
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if (chip->irq_ack)
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chip->irq_ack(&desc->irq_data);
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}
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}
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static inline void chained_irq_exit(struct irq_chip *chip,
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struct irq_desc *desc)
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{
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if (chip->irq_eoi)
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chip->irq_eoi(&desc->irq_data);
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else
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chip->irq_unmask(&desc->irq_data);
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}
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#endif
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#endif
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@ -22,10 +22,9 @@
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#include <linux/module.h>
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#include <linux/io.h>
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#include <linux/irqdomain.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/of_address.h>
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#include <asm/mach/irq.h>
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#include <mach/hardware.h>
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#include <mach/at91_pio.h>
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@ -26,6 +26,7 @@
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#include <linux/irqchip.h>
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#include <linux/of_address.h>
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#include <linux/irqchip/arm-gic.h>
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#include <linux/irqchip/chained_irq.h>
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#include <asm/proc-fns.h>
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#include <asm/exception.h>
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@ -20,7 +20,6 @@
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#include <linux/jiffies.h>
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#include <linux/smp.h>
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#include <linux/io.h>
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#include <linux/irqchip/arm-gic.h>
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#include <asm/cacheflush.h>
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#include <asm/smp_plat.h>
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@ -75,13 +74,6 @@ static DEFINE_SPINLOCK(boot_lock);
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static void __cpuinit exynos_secondary_init(unsigned int cpu)
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{
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/*
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* if any interrupts are already enabled for the primary
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* core (e.g. timer irq), then they will not have been enabled
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* for us: do so
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*/
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gic_secondary_init(0);
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/*
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* let the primary processor know we're out of the
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* pen, then head off into the C entry point
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@ -17,7 +17,6 @@
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#include <linux/init.h>
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#include <linux/smp.h>
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#include <linux/io.h>
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#include <linux/irqchip/arm-gic.h>
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#include <asm/smp_scu.h>
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@ -25,11 +24,6 @@
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extern void secondary_startup(void);
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static void __cpuinit highbank_secondary_init(unsigned int cpu)
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{
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gic_secondary_init(0);
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}
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static int __cpuinit highbank_boot_secondary(unsigned int cpu, struct task_struct *idle)
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{
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highbank_set_cpu_jump(cpu, secondary_startup);
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@ -67,7 +61,6 @@ static void __init highbank_smp_prepare_cpus(unsigned int max_cpus)
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struct smp_operations highbank_smp_ops __initdata = {
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.smp_init_cpus = highbank_smp_init_cpus,
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.smp_prepare_cpus = highbank_smp_prepare_cpus,
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.smp_secondary_init = highbank_secondary_init,
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.smp_boot_secondary = highbank_boot_secondary,
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#ifdef CONFIG_HOTPLUG_CPU
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.cpu_die = highbank_cpu_die,
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@ -12,7 +12,6 @@
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#include <linux/init.h>
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#include <linux/smp.h>
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#include <linux/irqchip/arm-gic.h>
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#include <asm/page.h>
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#include <asm/smp_scu.h>
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#include <asm/mach/map.h>
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@ -52,16 +51,6 @@ void imx_scu_standby_enable(void)
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writel_relaxed(val, scu_base);
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}
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static void __cpuinit imx_secondary_init(unsigned int cpu)
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{
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/*
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* if any interrupts are already enabled for the primary
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* core (e.g. timer irq), then they will not have been enabled
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* for us: do so
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*/
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gic_secondary_init(0);
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}
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static int __cpuinit imx_boot_secondary(unsigned int cpu, struct task_struct *idle)
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{
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imx_set_cpu_jump(cpu, v7_secondary_startup);
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@ -96,7 +85,6 @@ static void __init imx_smp_prepare_cpus(unsigned int max_cpus)
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struct smp_operations imx_smp_ops __initdata = {
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.smp_init_cpus = imx_smp_init_cpus,
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.smp_prepare_cpus = imx_smp_prepare_cpus,
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.smp_secondary_init = imx_secondary_init,
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.smp_boot_secondary = imx_boot_secondary,
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#ifdef CONFIG_HOTPLUG_CPU
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.cpu_die = imx_cpu_die,
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@ -15,7 +15,6 @@
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#include <linux/jiffies.h>
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#include <linux/smp.h>
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#include <linux/io.h>
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#include <linux/irqchip/arm-gic.h>
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#include <asm/cacheflush.h>
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#include <asm/cputype.h>
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@ -41,13 +40,6 @@ static inline int get_core_count(void)
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static void __cpuinit msm_secondary_init(unsigned int cpu)
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{
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/*
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* if any interrupts are already enabled for the primary
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* core (e.g. timer irq), then they will not have been enabled
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* for us: do so
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*/
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gic_secondary_init(0);
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/*
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* let the primary processor know we're out of the
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* pen, then head off into the C entry point
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@ -66,13 +66,6 @@ static void __cpuinit omap4_secondary_init(unsigned int cpu)
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omap_secure_dispatcher(OMAP4_PPA_CPU_ACTRL_SMP_INDEX,
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4, 0, 0, 0, 0, 0);
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/*
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* If any interrupts are already enabled for the primary
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* core (e.g. timer irq), then they will not have been enabled
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* for us: do so
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*/
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gic_secondary_init(0);
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/*
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* Synchronise with the boot thread.
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*/
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@ -11,7 +11,6 @@
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#include <linux/delay.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/irqchip/arm-gic.h>
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#include <asm/page.h>
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#include <asm/mach/map.h>
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#include <asm/smp_plat.h>
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@ -48,13 +47,6 @@ void __init sirfsoc_map_scu(void)
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static void __cpuinit sirfsoc_secondary_init(unsigned int cpu)
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{
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/*
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* if any interrupts are already enabled for the primary
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* core (e.g. timer irq), then they will not have been enabled
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* for us: do so
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*/
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gic_secondary_init(0);
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/*
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* let the primary processor know we're out of the
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* pen, then head off into the C entry point
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@ -25,6 +25,7 @@
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#include <linux/ioport.h>
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#include <linux/device.h>
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#include <linux/irqdomain.h>
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#include <linux/irqchip/chained_irq.h>
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#include <asm/mach/irq.h>
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@ -23,7 +23,6 @@
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#include <linux/spinlock.h>
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#include <linux/io.h>
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#include <linux/delay.h>
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#include <linux/irqchip/arm-gic.h>
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#include <mach/common.h>
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#include <mach/emev2.h>
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#include <asm/smp_plat.h>
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@ -31,11 +30,6 @@
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#define EMEV2_SCU_BASE 0x1e000000
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static void __cpuinit emev2_secondary_init(unsigned int cpu)
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{
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gic_secondary_init(0);
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}
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static int __cpuinit emev2_boot_secondary(unsigned int cpu, struct task_struct *idle)
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{
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arch_send_wakeup_ipi_mask(cpumask_of(cpu_logical_map(cpu)));
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@ -69,6 +63,5 @@ static void __init emev2_smp_init_cpus(void)
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struct smp_operations emev2_smp_ops __initdata = {
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.smp_init_cpus = emev2_smp_init_cpus,
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.smp_prepare_cpus = emev2_smp_prepare_cpus,
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.smp_secondary_init = emev2_secondary_init,
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.smp_boot_secondary = emev2_boot_secondary,
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};
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@ -23,7 +23,6 @@
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#include <linux/spinlock.h>
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#include <linux/io.h>
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#include <linux/delay.h>
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#include <linux/irqchip/arm-gic.h>
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#include <mach/common.h>
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#include <mach/r8a7779.h>
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#include <asm/cacheflush.h>
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@ -82,11 +81,6 @@ static int r8a7779_platform_cpu_kill(unsigned int cpu)
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return ret ? ret : 1;
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}
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static void __cpuinit r8a7779_secondary_init(unsigned int cpu)
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{
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gic_secondary_init(0);
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}
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static int __cpuinit r8a7779_boot_secondary(unsigned int cpu, struct task_struct *idle)
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{
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struct r8a7779_pm_ch *ch = NULL;
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|
@ -181,7 +175,6 @@ static int r8a7779_cpu_disable(unsigned int cpu)
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struct smp_operations r8a7779_smp_ops __initdata = {
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.smp_init_cpus = r8a7779_smp_init_cpus,
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.smp_prepare_cpus = r8a7779_smp_prepare_cpus,
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.smp_secondary_init = r8a7779_secondary_init,
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.smp_boot_secondary = r8a7779_boot_secondary,
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#ifdef CONFIG_HOTPLUG_CPU
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.cpu_kill = r8a7779_cpu_kill,
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|
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|
@ -23,7 +23,6 @@
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#include <linux/spinlock.h>
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#include <linux/io.h>
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#include <linux/delay.h>
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#include <linux/irqchip/arm-gic.h>
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#include <mach/common.h>
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#include <asm/cacheflush.h>
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#include <asm/smp_plat.h>
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|
@ -49,11 +48,6 @@ void __init sh73a0_register_twd(void)
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}
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#endif
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static void __cpuinit sh73a0_secondary_init(unsigned int cpu)
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{
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gic_secondary_init(0);
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}
|
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|
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static int __cpuinit sh73a0_boot_secondary(unsigned int cpu, struct task_struct *idle)
|
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{
|
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cpu = cpu_logical_map(cpu);
|
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|
@ -134,7 +128,6 @@ static int sh73a0_cpu_disable(unsigned int cpu)
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struct smp_operations sh73a0_smp_ops __initdata = {
|
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.smp_init_cpus = sh73a0_smp_init_cpus,
|
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.smp_prepare_cpus = sh73a0_smp_prepare_cpus,
|
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.smp_secondary_init = sh73a0_secondary_init,
|
||||
.smp_boot_secondary = sh73a0_boot_secondary,
|
||||
#ifdef CONFIG_HOTPLUG_CPU
|
||||
.cpu_kill = sh73a0_cpu_kill,
|
||||
|
|
|
@ -22,7 +22,6 @@
|
|||
#include <linux/io.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/irqchip/arm-gic.h>
|
||||
|
||||
#include <asm/cacheflush.h>
|
||||
#include <asm/smp_scu.h>
|
||||
|
@ -33,16 +32,6 @@
|
|||
extern void __iomem *sys_manager_base_addr;
|
||||
extern void __iomem *rst_manager_base_addr;
|
||||
|
||||
static void __cpuinit socfpga_secondary_init(unsigned int cpu)
|
||||
{
|
||||
/*
|
||||
* if any interrupts are already enabled for the primary
|
||||
* core (e.g. timer irq), then they will not have been enabled
|
||||
* for us: do so
|
||||
*/
|
||||
gic_secondary_init(0);
|
||||
}
|
||||
|
||||
static int __cpuinit socfpga_boot_secondary(unsigned int cpu, struct task_struct *idle)
|
||||
{
|
||||
int trampoline_size = &secondary_trampoline_end - &secondary_trampoline;
|
||||
|
@ -109,7 +98,6 @@ static void socfpga_cpu_die(unsigned int cpu)
|
|||
struct smp_operations socfpga_smp_ops __initdata = {
|
||||
.smp_init_cpus = socfpga_smp_init_cpus,
|
||||
.smp_prepare_cpus = socfpga_smp_prepare_cpus,
|
||||
.smp_secondary_init = socfpga_secondary_init,
|
||||
.smp_boot_secondary = socfpga_boot_secondary,
|
||||
#ifdef CONFIG_HOTPLUG_CPU
|
||||
.cpu_die = socfpga_cpu_die,
|
||||
|
|
|
@ -15,7 +15,6 @@
|
|||
#include <linux/jiffies.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/smp.h>
|
||||
#include <linux/irqchip/arm-gic.h>
|
||||
#include <asm/cacheflush.h>
|
||||
#include <asm/smp_scu.h>
|
||||
#include <mach/spear.h>
|
||||
|
@ -27,13 +26,6 @@ static void __iomem *scu_base = IOMEM(VA_SCU_BASE);
|
|||
|
||||
static void __cpuinit spear13xx_secondary_init(unsigned int cpu)
|
||||
{
|
||||
/*
|
||||
* if any interrupts are already enabled for the primary
|
||||
* core (e.g. timer irq), then they will not have been enabled
|
||||
* for us: do so
|
||||
*/
|
||||
gic_secondary_init(0);
|
||||
|
||||
/*
|
||||
* let the primary processor know we're out of the
|
||||
* pen, then head off into the C entry point
|
||||
|
|
|
@ -18,7 +18,6 @@
|
|||
#include <linux/jiffies.h>
|
||||
#include <linux/smp.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/irqchip/arm-gic.h>
|
||||
#include <linux/clk/tegra.h>
|
||||
|
||||
#include <asm/cacheflush.h>
|
||||
|
@ -44,13 +43,6 @@ static cpumask_t tegra_cpu_init_mask;
|
|||
|
||||
static void __cpuinit tegra_secondary_init(unsigned int cpu)
|
||||
{
|
||||
/*
|
||||
* if any interrupts are already enabled for the primary
|
||||
* core (e.g. timer irq), then they will not have been enabled
|
||||
* for us: do so
|
||||
*/
|
||||
gic_secondary_init(0);
|
||||
|
||||
cpumask_set_cpu(cpu, &tegra_cpu_init_mask);
|
||||
}
|
||||
|
||||
|
|
|
@ -16,7 +16,6 @@
|
|||
#include <linux/device.h>
|
||||
#include <linux/smp.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/irqchip/arm-gic.h>
|
||||
|
||||
#include <asm/cacheflush.h>
|
||||
#include <asm/smp_plat.h>
|
||||
|
@ -57,13 +56,6 @@ static DEFINE_SPINLOCK(boot_lock);
|
|||
|
||||
static void __cpuinit ux500_secondary_init(unsigned int cpu)
|
||||
{
|
||||
/*
|
||||
* if any interrupts are already enabled for the primary
|
||||
* core (e.g. timer irq), then they will not have been enabled
|
||||
* for us: do so
|
||||
*/
|
||||
gic_secondary_init(0);
|
||||
|
||||
/*
|
||||
* let the primary processor know we're out of the
|
||||
* pen, then head off into the C entry point
|
||||
|
|
|
@ -21,8 +21,6 @@
|
|||
#include <linux/smp.h>
|
||||
#include <linux/of.h>
|
||||
|
||||
#include <linux/irqchip/arm-gic.h>
|
||||
|
||||
#include <asm/psci.h>
|
||||
#include <asm/smp_plat.h>
|
||||
|
||||
|
@ -45,14 +43,8 @@ static int __cpuinit virt_boot_secondary(unsigned int cpu,
|
|||
return -ENODEV;
|
||||
}
|
||||
|
||||
static void __cpuinit virt_secondary_init(unsigned int cpu)
|
||||
{
|
||||
gic_secondary_init(0);
|
||||
}
|
||||
|
||||
struct smp_operations __initdata virt_smp_ops = {
|
||||
.smp_init_cpus = virt_smp_init_cpus,
|
||||
.smp_prepare_cpus = virt_smp_prepare_cpus,
|
||||
.smp_secondary_init = virt_secondary_init,
|
||||
.smp_boot_secondary = virt_boot_secondary,
|
||||
};
|
||||
|
|
|
@ -34,21 +34,6 @@
|
|||
*/
|
||||
static int ncores;
|
||||
|
||||
/* Secondary CPU kernel startup is a 2 step process. The primary CPU
|
||||
* starts the secondary CPU by giving it the address of the kernel and
|
||||
* then sending it an event to wake it up. The secondary CPU then
|
||||
* starts the kernel and tells the primary CPU it's up and running.
|
||||
*/
|
||||
static void __cpuinit zynq_secondary_init(unsigned int cpu)
|
||||
{
|
||||
/*
|
||||
* if any interrupts are already enabled for the primary
|
||||
* core (e.g. timer irq), then they will not have been enabled
|
||||
* for us: do so
|
||||
*/
|
||||
gic_secondary_init(0);
|
||||
}
|
||||
|
||||
int __cpuinit zynq_cpun_start(u32 address, int cpu)
|
||||
{
|
||||
u32 trampoline_code_size = &zynq_secondary_trampoline_end -
|
||||
|
@ -144,7 +129,6 @@ static void __init zynq_smp_prepare_cpus(unsigned int max_cpus)
|
|||
struct smp_operations zynq_smp_ops __initdata = {
|
||||
.smp_init_cpus = zynq_smp_init_cpus,
|
||||
.smp_prepare_cpus = zynq_smp_prepare_cpus,
|
||||
.smp_secondary_init = zynq_secondary_init,
|
||||
.smp_boot_secondary = zynq_boot_secondary,
|
||||
#ifdef CONFIG_HOTPLUG_CPU
|
||||
.cpu_die = zynq_platform_cpu_die,
|
||||
|
|
|
@ -16,6 +16,7 @@
|
|||
#include <linux/kernel.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/irqchip/chained_irq.h>
|
||||
#include <linux/io.h>
|
||||
|
||||
#include <mach/map.h>
|
||||
|
@ -23,8 +24,6 @@
|
|||
#include <plat/irq-vic-timer.h>
|
||||
#include <plat/regs-timer.h>
|
||||
|
||||
#include <asm/mach/irq.h>
|
||||
|
||||
static void s3c_irq_demux_vic_timer(unsigned int irq, struct irq_desc *desc)
|
||||
{
|
||||
struct irq_chip *chip = irq_get_chip(irq);
|
||||
|
|
|
@ -14,6 +14,7 @@
|
|||
#include <linux/kernel.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/irqchip/chained_irq.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/slab.h>
|
||||
|
@ -22,8 +23,6 @@
|
|||
#include <plat/gpio-core.h>
|
||||
#include <plat/gpio-cfg.h>
|
||||
|
||||
#include <asm/mach/irq.h>
|
||||
|
||||
#define GPIO_BASE(chip) ((void __iomem *)((unsigned long)((chip)->base) & 0xFFFFF000u))
|
||||
|
||||
#define CON_OFFSET 0x700
|
||||
|
|
|
@ -14,7 +14,6 @@
|
|||
#include <linux/device.h>
|
||||
#include <linux/jiffies.h>
|
||||
#include <linux/smp.h>
|
||||
#include <linux/irqchip/arm-gic.h>
|
||||
|
||||
#include <asm/cacheflush.h>
|
||||
#include <asm/smp_plat.h>
|
||||
|
@ -36,13 +35,6 @@ static DEFINE_SPINLOCK(boot_lock);
|
|||
|
||||
void __cpuinit versatile_secondary_init(unsigned int cpu)
|
||||
{
|
||||
/*
|
||||
* if any interrupts are already enabled for the primary
|
||||
* core (e.g. timer irq), then they will not have been enabled
|
||||
* for us: do so
|
||||
*/
|
||||
gic_secondary_init(0);
|
||||
|
||||
/*
|
||||
* let the primary processor know we're out of the
|
||||
* pen, then head off into the C entry point
|
||||
|
|
|
@ -23,13 +23,12 @@
|
|||
#include <linux/init.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/irqchip/chained_irq.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/spinlock.h>
|
||||
|
||||
#include <asm/mach/irq.h>
|
||||
|
||||
#include <mach/msm_gpiomux.h>
|
||||
#include <mach/msm_iomap.h>
|
||||
|
||||
|
|
|
@ -24,6 +24,7 @@
|
|||
#include <linux/io.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/irqdomain.h>
|
||||
#include <linux/irqchip/chained_irq.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/slab.h>
|
||||
|
@ -32,7 +33,6 @@
|
|||
#include <linux/of_device.h>
|
||||
#include <linux/module.h>
|
||||
#include <asm-generic/bug.h>
|
||||
#include <asm/mach/irq.h>
|
||||
|
||||
enum mxc_gpio_hwtype {
|
||||
IMX1_GPIO, /* runs on i.mx1 */
|
||||
|
|
|
@ -25,11 +25,10 @@
|
|||
#include <linux/of.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/irqdomain.h>
|
||||
#include <linux/irqchip/chained_irq.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/platform_data/gpio-omap.h>
|
||||
|
||||
#include <asm/mach/irq.h>
|
||||
|
||||
#define OFF_MODE 1
|
||||
|
||||
static LIST_HEAD(omap_gpio_list);
|
||||
|
|
|
@ -15,6 +15,7 @@
|
|||
#include <linux/io.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/irqchip/chained_irq.h>
|
||||
#include <linux/irqdomain.h>
|
||||
#include <linux/bitops.h>
|
||||
#include <linux/workqueue.h>
|
||||
|
@ -25,7 +26,6 @@
|
|||
#include <linux/slab.h>
|
||||
#include <linux/pinctrl/consumer.h>
|
||||
#include <linux/pm.h>
|
||||
#include <asm/mach/irq.h>
|
||||
|
||||
#define GPIODIR 0x400
|
||||
#define GPIOIS 0x404
|
||||
|
|
|
@ -19,6 +19,7 @@
|
|||
#include <linux/init.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/irqdomain.h>
|
||||
#include <linux/irqchip/chained_irq.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_device.h>
|
||||
|
@ -26,8 +27,6 @@
|
|||
#include <linux/syscore_ops.h>
|
||||
#include <linux/slab.h>
|
||||
|
||||
#include <asm/mach/irq.h>
|
||||
|
||||
#include <mach/irqs.h>
|
||||
|
||||
/*
|
||||
|
|
|
@ -27,11 +27,10 @@
|
|||
#include <linux/platform_device.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/irqdomain.h>
|
||||
#include <linux/irqchip/chained_irq.h>
|
||||
#include <linux/pinctrl/consumer.h>
|
||||
#include <linux/pm.h>
|
||||
|
||||
#include <asm/mach/irq.h>
|
||||
|
||||
#define GPIO_BANK(x) ((x) >> 5)
|
||||
#define GPIO_PORT(x) (((x) >> 3) & 0x3)
|
||||
#define GPIO_BIT(x) ((x) & 0x7)
|
||||
|
|
|
@ -13,6 +13,7 @@
|
|||
#include <linux/init.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/irqdomain.h>
|
||||
#include <linux/irqchip/chained_irq.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_irq.h>
|
||||
#include <asm/mach/irq.h>
|
||||
|
|
|
@ -28,6 +28,7 @@
|
|||
#include <linux/module.h>
|
||||
#include <linux/list.h>
|
||||
#include <linux/smp.h>
|
||||
#include <linux/cpu.h>
|
||||
#include <linux/cpu_pm.h>
|
||||
#include <linux/cpumask.h>
|
||||
#include <linux/io.h>
|
||||
|
@ -38,12 +39,12 @@
|
|||
#include <linux/interrupt.h>
|
||||
#include <linux/percpu.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/irqchip/chained_irq.h>
|
||||
#include <linux/irqchip/arm-gic.h>
|
||||
|
||||
#include <asm/irq.h>
|
||||
#include <asm/exception.h>
|
||||
#include <asm/smp_plat.h>
|
||||
#include <asm/mach/irq.h>
|
||||
|
||||
#include "irqchip.h"
|
||||
|
||||
|
@ -323,7 +324,7 @@ static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
|
|||
|
||||
cascade_irq = irq_find_mapping(chip_data->domain, gic_irq);
|
||||
if (unlikely(gic_irq < 32 || gic_irq > 1020))
|
||||
do_bad_IRQ(cascade_irq, desc);
|
||||
handle_bad_irq(cascade_irq, desc);
|
||||
else
|
||||
generic_handle_irq(cascade_irq);
|
||||
|
||||
|
@ -699,6 +700,25 @@ static int gic_irq_domain_xlate(struct irq_domain *d,
|
|||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
static int __cpuinit gic_secondary_init(struct notifier_block *nfb,
|
||||
unsigned long action, void *hcpu)
|
||||
{
|
||||
if (action == CPU_STARTING)
|
||||
gic_cpu_init(&gic_data[0]);
|
||||
return NOTIFY_OK;
|
||||
}
|
||||
|
||||
/*
|
||||
* Notifier for enabling the GIC CPU interface. Set an arbitrarily high
|
||||
* priority because the GIC needs to be up before the ARM generic timers.
|
||||
*/
|
||||
static struct notifier_block __cpuinitdata gic_cpu_notifier = {
|
||||
.notifier_call = gic_secondary_init,
|
||||
.priority = 100,
|
||||
};
|
||||
#endif
|
||||
|
||||
const struct irq_domain_ops gic_irq_domain_ops = {
|
||||
.map = gic_irq_domain_map,
|
||||
.xlate = gic_irq_domain_xlate,
|
||||
|
@ -789,6 +809,7 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start,
|
|||
|
||||
#ifdef CONFIG_SMP
|
||||
set_smp_cross_call(gic_raise_softirq);
|
||||
register_cpu_notifier(&gic_cpu_notifier);
|
||||
#endif
|
||||
|
||||
set_handle_irq(gic_handle_irq);
|
||||
|
@ -799,13 +820,6 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start,
|
|||
gic_pm_init(gic);
|
||||
}
|
||||
|
||||
void __cpuinit gic_secondary_init(unsigned int gic_nr)
|
||||
{
|
||||
BUG_ON(gic_nr >= MAX_GIC_NR);
|
||||
|
||||
gic_cpu_init(&gic_data[gic_nr]);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_OF
|
||||
static int gic_cnt __initdata = 0;
|
||||
|
||||
|
|
|
@ -23,6 +23,7 @@
|
|||
#include <linux/init.h>
|
||||
#include <linux/list.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/irqdomain.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
|
@ -33,7 +34,7 @@
|
|||
#include <linux/irqchip/arm-vic.h>
|
||||
|
||||
#include <asm/exception.h>
|
||||
#include <asm/mach/irq.h>
|
||||
#include <asm/irq.h>
|
||||
|
||||
#include "irqchip.h"
|
||||
|
||||
|
|
|
@ -18,6 +18,7 @@
|
|||
#include <linux/interrupt.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/irqdomain.h>
|
||||
#include <linux/irqchip/chained_irq.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/pinctrl/machine.h>
|
||||
|
@ -27,8 +28,6 @@
|
|||
/* Since we request GPIOs from ourself */
|
||||
#include <linux/pinctrl/consumer.h>
|
||||
|
||||
#include <asm/mach/irq.h>
|
||||
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/at91_pio.h>
|
||||
|
||||
|
|
|
@ -23,13 +23,12 @@
|
|||
#include <linux/interrupt.h>
|
||||
#include <linux/irqdomain.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/irqchip/chained_irq.h>
|
||||
#include <linux/of_irq.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/err.h>
|
||||
|
||||
#include <asm/mach/irq.h>
|
||||
|
||||
#include "pinctrl-samsung.h"
|
||||
#include "pinctrl-exynos.h"
|
||||
|
||||
|
|
|
@ -23,6 +23,7 @@
|
|||
#include <linux/interrupt.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/irqdomain.h>
|
||||
#include <linux/irqchip/chained_irq.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/of_address.h>
|
||||
|
@ -33,7 +34,6 @@
|
|||
/* Since we request GPIOs from ourself */
|
||||
#include <linux/pinctrl/consumer.h>
|
||||
#include <linux/platform_data/pinctrl-nomadik.h>
|
||||
#include <asm/mach/irq.h>
|
||||
#include "pinctrl-nomadik.h"
|
||||
#include "core.h"
|
||||
|
||||
|
|
|
@ -14,6 +14,7 @@
|
|||
#include <linux/slab.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/irqdomain.h>
|
||||
#include <linux/irqchip/chained_irq.h>
|
||||
#include <linux/pinctrl/pinctrl.h>
|
||||
#include <linux/pinctrl/pinmux.h>
|
||||
#include <linux/pinctrl/consumer.h>
|
||||
|
@ -25,7 +26,6 @@
|
|||
#include <linux/bitops.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/of_gpio.h>
|
||||
#include <asm/mach/irq.h>
|
||||
|
||||
#define DRIVER_NAME "pinmux-sirf"
|
||||
|
||||
|
|
|
@ -15,12 +15,12 @@
|
|||
#include <linux/io.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/irqdomain.h>
|
||||
#include <linux/irqchip/chained_irq.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/pinctrl/consumer.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/pm.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <asm/mach/irq.h>
|
||||
|
||||
#define MAX_GPIO_PER_REG 32
|
||||
#define PIN_OFFSET(pin) (pin % MAX_GPIO_PER_REG)
|
||||
|
|
|
@ -25,8 +25,8 @@
|
|||
#include <linux/clk.h>
|
||||
#include <linux/list.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/irqchip/chained_irq.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <asm/mach/irq.h>
|
||||
|
||||
#include "imx-ipu-v3.h"
|
||||
#include "ipu-prv.h"
|
||||
|
|
|
@ -65,7 +65,6 @@ extern struct irq_chip gic_arch_extn;
|
|||
|
||||
void gic_init_bases(unsigned int, int, void __iomem *, void __iomem *,
|
||||
u32 offset, struct device_node *);
|
||||
void gic_secondary_init(unsigned int);
|
||||
void gic_cascade_irq(unsigned int gic_nr, unsigned int irq);
|
||||
|
||||
static inline void gic_init(unsigned int nr, int start,
|
||||
|
|
52
include/linux/irqchip/chained_irq.h
Normal file
52
include/linux/irqchip/chained_irq.h
Normal file
|
@ -0,0 +1,52 @@
|
|||
/*
|
||||
* Chained IRQ handlers support.
|
||||
*
|
||||
* Copyright (C) 2011 ARM Ltd.
|
||||
*
|
||||
* This program is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
#ifndef __IRQCHIP_CHAINED_IRQ_H
|
||||
#define __IRQCHIP_CHAINED_IRQ_H
|
||||
|
||||
#include <linux/irq.h>
|
||||
|
||||
/*
|
||||
* Entry/exit functions for chained handlers where the primary IRQ chip
|
||||
* may implement either fasteoi or level-trigger flow control.
|
||||
*/
|
||||
static inline void chained_irq_enter(struct irq_chip *chip,
|
||||
struct irq_desc *desc)
|
||||
{
|
||||
/* FastEOI controllers require no action on entry. */
|
||||
if (chip->irq_eoi)
|
||||
return;
|
||||
|
||||
if (chip->irq_mask_ack) {
|
||||
chip->irq_mask_ack(&desc->irq_data);
|
||||
} else {
|
||||
chip->irq_mask(&desc->irq_data);
|
||||
if (chip->irq_ack)
|
||||
chip->irq_ack(&desc->irq_data);
|
||||
}
|
||||
}
|
||||
|
||||
static inline void chained_irq_exit(struct irq_chip *chip,
|
||||
struct irq_desc *desc)
|
||||
{
|
||||
if (chip->irq_eoi)
|
||||
chip->irq_eoi(&desc->irq_data);
|
||||
else
|
||||
chip->irq_unmask(&desc->irq_data);
|
||||
}
|
||||
|
||||
#endif /* __IRQCHIP_CHAINED_IRQ_H */
|
Loading…
Reference in a new issue