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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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habanalabs: remove debugfs read/write callbacks
The debugfs memory access now uses the callback 'access_dev_mem'
so there is no use of the callbacks
'debugfs_{read32,read64,write32,write6}'. Remove them.
Signed-off-by: Dafna Hirschfeld <dhirschfeld@habana.ai>
Reviewed-by: Oded Gabbay <ogabbay@kernel.org>
Signed-off-by: Oded Gabbay <ogabbay@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Dafna Hirschfeld
Greg Kroah-Hartman
parent
9248aa90d2
commit
799b9eb01a
3 changed files with 1 additions and 416 deletions
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@ -1282,10 +1282,6 @@ struct fw_load_mgr {
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* @update_eq_ci: update event queue CI.
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* @context_switch: called upon ASID context switch.
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* @restore_phase_topology: clear all SOBs amd MONs.
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* @debugfs_read32: debug interface for reading u32 from DRAM/SRAM/Host memory.
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* @debugfs_write32: debug interface for writing u32 to DRAM/SRAM/Host memory.
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* @debugfs_read64: debug interface for reading u64 from DRAM/SRAM/Host memory.
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* @debugfs_write64: debug interface for writing u64 to DRAM/SRAM/Host memory.
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* @debugfs_read_dma: debug interface for reading up to 2MB from the device's
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* internal memory via DMA engine.
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* @add_device_attr: add ASIC specific device attributes.
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@ -1409,14 +1405,6 @@ struct hl_asic_funcs {
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void (*update_eq_ci)(struct hl_device *hdev, u32 val);
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int (*context_switch)(struct hl_device *hdev, u32 asid);
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void (*restore_phase_topology)(struct hl_device *hdev);
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int (*debugfs_read32)(struct hl_device *hdev, u64 addr,
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bool user_address, u32 *val);
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int (*debugfs_write32)(struct hl_device *hdev, u64 addr,
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bool user_address, u32 val);
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int (*debugfs_read64)(struct hl_device *hdev, u64 addr,
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bool user_address, u64 *val);
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int (*debugfs_write64)(struct hl_device *hdev, u64 addr,
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bool user_address, u64 val);
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int (*debugfs_read_dma)(struct hl_device *hdev, u64 addr, u32 size,
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void *blob_addr);
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void (*add_device_attr)(struct hl_device *hdev, struct attribute_group *dev_clk_attr_grp,
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@ -6104,184 +6104,6 @@ static void gaudi_restore_phase_topology(struct hl_device *hdev)
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}
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static int gaudi_debugfs_read32(struct hl_device *hdev, u64 addr,
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bool user_address, u32 *val)
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{
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struct asic_fixed_properties *prop = &hdev->asic_prop;
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u64 hbm_bar_addr, host_phys_end;
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int rc = 0;
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host_phys_end = HOST_PHYS_BASE + HOST_PHYS_SIZE;
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if ((addr >= CFG_BASE) && (addr < CFG_BASE + CFG_SIZE)) {
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*val = RREG32(addr - CFG_BASE);
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} else if ((addr >= SRAM_BASE_ADDR) && (addr < SRAM_BASE_ADDR + SRAM_SIZE)) {
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*val = readl(hdev->pcie_bar[SRAM_BAR_ID] + (addr - SRAM_BASE_ADDR));
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} else if (addr < DRAM_PHYS_BASE + hdev->asic_prop.dram_size) {
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u64 bar_base_addr = DRAM_PHYS_BASE + (addr & ~(prop->dram_pci_bar_size - 0x1ull));
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hbm_bar_addr = gaudi_set_hbm_bar_base(hdev, bar_base_addr);
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if (hbm_bar_addr != U64_MAX) {
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*val = readl(hdev->pcie_bar[HBM_BAR_ID] + (addr - bar_base_addr));
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hbm_bar_addr = gaudi_set_hbm_bar_base(hdev, hbm_bar_addr);
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}
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if (hbm_bar_addr == U64_MAX)
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rc = -EIO;
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} else if (addr >= HOST_PHYS_BASE && addr < host_phys_end &&
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user_address && !iommu_present(&pci_bus_type)) {
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*val = *(u32 *) phys_to_virt(addr - HOST_PHYS_BASE);
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} else {
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rc = -EFAULT;
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}
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return rc;
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}
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static int gaudi_debugfs_write32(struct hl_device *hdev, u64 addr,
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bool user_address, u32 val)
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{
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struct asic_fixed_properties *prop = &hdev->asic_prop;
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u64 hbm_bar_addr, host_phys_end;
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int rc = 0;
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host_phys_end = HOST_PHYS_BASE + HOST_PHYS_SIZE;
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if ((addr >= CFG_BASE) && (addr < CFG_BASE + CFG_SIZE)) {
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WREG32(addr - CFG_BASE, val);
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} else if ((addr >= SRAM_BASE_ADDR) && (addr < SRAM_BASE_ADDR + SRAM_SIZE)) {
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writel(val, hdev->pcie_bar[SRAM_BAR_ID] + (addr - SRAM_BASE_ADDR));
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} else if (addr < DRAM_PHYS_BASE + hdev->asic_prop.dram_size) {
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u64 bar_base_addr = DRAM_PHYS_BASE + (addr & ~(prop->dram_pci_bar_size - 0x1ull));
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hbm_bar_addr = gaudi_set_hbm_bar_base(hdev, bar_base_addr);
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if (hbm_bar_addr != U64_MAX) {
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writel(val, hdev->pcie_bar[HBM_BAR_ID] + (addr - bar_base_addr));
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hbm_bar_addr = gaudi_set_hbm_bar_base(hdev, hbm_bar_addr);
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}
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if (hbm_bar_addr == U64_MAX)
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rc = -EIO;
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} else if (addr >= HOST_PHYS_BASE && addr < host_phys_end &&
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user_address && !iommu_present(&pci_bus_type)) {
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*(u32 *) phys_to_virt(addr - HOST_PHYS_BASE) = val;
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} else {
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rc = -EFAULT;
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}
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return rc;
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}
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static int gaudi_debugfs_read64(struct hl_device *hdev, u64 addr,
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bool user_address, u64 *val)
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{
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struct asic_fixed_properties *prop = &hdev->asic_prop;
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u64 hbm_bar_addr, host_phys_end;
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int rc = 0;
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host_phys_end = HOST_PHYS_BASE + HOST_PHYS_SIZE;
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if ((addr >= CFG_BASE) && (addr <= CFG_BASE + CFG_SIZE - sizeof(u64))) {
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u32 val_l = RREG32(addr - CFG_BASE);
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u32 val_h = RREG32(addr + sizeof(u32) - CFG_BASE);
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*val = (((u64) val_h) << 32) | val_l;
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} else if ((addr >= SRAM_BASE_ADDR) &&
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(addr <= SRAM_BASE_ADDR + SRAM_SIZE - sizeof(u64))) {
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*val = readq(hdev->pcie_bar[SRAM_BAR_ID] + (addr - SRAM_BASE_ADDR));
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} else if (addr <= DRAM_PHYS_BASE + hdev->asic_prop.dram_size - sizeof(u64)) {
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u64 bar_base_addr = DRAM_PHYS_BASE + (addr & ~(prop->dram_pci_bar_size - 0x1ull));
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hbm_bar_addr = gaudi_set_hbm_bar_base(hdev, bar_base_addr);
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if (hbm_bar_addr != U64_MAX) {
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*val = readq(hdev->pcie_bar[HBM_BAR_ID] + (addr - bar_base_addr));
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hbm_bar_addr = gaudi_set_hbm_bar_base(hdev, hbm_bar_addr);
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}
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if (hbm_bar_addr == U64_MAX)
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rc = -EIO;
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} else if (addr >= HOST_PHYS_BASE && addr < host_phys_end &&
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user_address && !iommu_present(&pci_bus_type)) {
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*val = *(u64 *) phys_to_virt(addr - HOST_PHYS_BASE);
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} else {
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rc = -EFAULT;
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}
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return rc;
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}
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static int gaudi_debugfs_write64(struct hl_device *hdev, u64 addr,
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bool user_address, u64 val)
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{
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struct asic_fixed_properties *prop = &hdev->asic_prop;
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u64 hbm_bar_addr, host_phys_end;
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int rc = 0;
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host_phys_end = HOST_PHYS_BASE + HOST_PHYS_SIZE;
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if ((addr >= CFG_BASE) && (addr <= CFG_BASE + CFG_SIZE - sizeof(u64))) {
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WREG32(addr - CFG_BASE, lower_32_bits(val));
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WREG32(addr + sizeof(u32) - CFG_BASE, upper_32_bits(val));
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} else if ((addr >= SRAM_BASE_ADDR) &&
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(addr <= SRAM_BASE_ADDR + SRAM_SIZE - sizeof(u64))) {
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writeq(val, hdev->pcie_bar[SRAM_BAR_ID] + (addr - SRAM_BASE_ADDR));
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} else if (addr <= DRAM_PHYS_BASE + hdev->asic_prop.dram_size - sizeof(u64)) {
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u64 bar_base_addr = DRAM_PHYS_BASE + (addr & ~(prop->dram_pci_bar_size - 0x1ull));
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hbm_bar_addr = gaudi_set_hbm_bar_base(hdev, bar_base_addr);
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if (hbm_bar_addr != U64_MAX) {
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writeq(val, hdev->pcie_bar[HBM_BAR_ID] + (addr - bar_base_addr));
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hbm_bar_addr = gaudi_set_hbm_bar_base(hdev, hbm_bar_addr);
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}
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if (hbm_bar_addr == U64_MAX)
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rc = -EIO;
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} else if (addr >= HOST_PHYS_BASE && addr < host_phys_end &&
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user_address && !iommu_present(&pci_bus_type)) {
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*(u64 *) phys_to_virt(addr - HOST_PHYS_BASE) = val;
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} else {
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rc = -EFAULT;
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}
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return rc;
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}
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static int gaudi_dma_core_transfer(struct hl_device *hdev, int dma_id, u64 addr,
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u32 size_to_dma, dma_addr_t dma_addr)
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{
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@ -9450,10 +9272,6 @@ static const struct hl_asic_funcs gaudi_funcs = {
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.update_eq_ci = gaudi_update_eq_ci,
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.context_switch = gaudi_context_switch,
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.restore_phase_topology = gaudi_restore_phase_topology,
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.debugfs_read32 = gaudi_debugfs_read32,
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.debugfs_write32 = gaudi_debugfs_write32,
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.debugfs_read64 = gaudi_debugfs_read64,
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.debugfs_write64 = gaudi_debugfs_write64,
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.debugfs_read_dma = gaudi_debugfs_read_dma,
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.add_device_attr = gaudi_add_device_attr,
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.handle_eqe = gaudi_handle_eqe,
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@ -4262,224 +4262,7 @@ static void goya_clear_sm_regs(struct hl_device *hdev)
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i = RREG32(mmSYNC_MNGR_SOB_OBJ_0);
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}
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/*
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* goya_debugfs_read32 - read a 32bit value from a given device or a host mapped
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* address.
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*
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* @hdev: pointer to hl_device structure
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* @addr: device or host mapped address
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* @val: returned value
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*
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* In case of DDR address that is not mapped into the default aperture that
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* the DDR bar exposes, the function will configure the iATU so that the DDR
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* bar will be positioned at a base address that allows reading from the
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* required address. Configuring the iATU during normal operation can
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* lead to undefined behavior and therefore, should be done with extreme care
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*
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*/
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static int goya_debugfs_read32(struct hl_device *hdev, u64 addr,
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bool user_address, u32 *val)
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{
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struct asic_fixed_properties *prop = &hdev->asic_prop;
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u64 ddr_bar_addr, host_phys_end;
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int rc = 0;
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host_phys_end = HOST_PHYS_BASE + HOST_PHYS_SIZE;
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if ((addr >= CFG_BASE) && (addr < CFG_BASE + CFG_SIZE)) {
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*val = RREG32(addr - CFG_BASE);
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} else if ((addr >= SRAM_BASE_ADDR) &&
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(addr < SRAM_BASE_ADDR + SRAM_SIZE)) {
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*val = readl(hdev->pcie_bar[SRAM_CFG_BAR_ID] +
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(addr - SRAM_BASE_ADDR));
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} else if (addr < DRAM_PHYS_BASE + hdev->asic_prop.dram_size) {
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u64 bar_base_addr = DRAM_PHYS_BASE +
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(addr & ~(prop->dram_pci_bar_size - 0x1ull));
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ddr_bar_addr = goya_set_ddr_bar_base(hdev, bar_base_addr);
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if (ddr_bar_addr != U64_MAX) {
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*val = readl(hdev->pcie_bar[DDR_BAR_ID] +
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(addr - bar_base_addr));
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ddr_bar_addr = goya_set_ddr_bar_base(hdev,
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ddr_bar_addr);
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}
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if (ddr_bar_addr == U64_MAX)
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rc = -EIO;
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} else if (addr >= HOST_PHYS_BASE && addr < host_phys_end &&
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user_address && !iommu_present(&pci_bus_type)) {
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*val = *(u32 *) phys_to_virt(addr - HOST_PHYS_BASE);
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} else {
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rc = -EFAULT;
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}
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return rc;
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}
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/*
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* goya_debugfs_write32 - write a 32bit value to a given device or a host mapped
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* address.
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*
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* @hdev: pointer to hl_device structure
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* @addr: device or host mapped address
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* @val: returned value
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*
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* In case of DDR address that is not mapped into the default aperture that
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* the DDR bar exposes, the function will configure the iATU so that the DDR
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* bar will be positioned at a base address that allows writing to the
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* required address. Configuring the iATU during normal operation can
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* lead to undefined behavior and therefore, should be done with extreme care
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*
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*/
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static int goya_debugfs_write32(struct hl_device *hdev, u64 addr,
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bool user_address, u32 val)
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{
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struct asic_fixed_properties *prop = &hdev->asic_prop;
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u64 ddr_bar_addr, host_phys_end;
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int rc = 0;
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host_phys_end = HOST_PHYS_BASE + HOST_PHYS_SIZE;
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if ((addr >= CFG_BASE) && (addr < CFG_BASE + CFG_SIZE)) {
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WREG32(addr - CFG_BASE, val);
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} else if ((addr >= SRAM_BASE_ADDR) &&
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(addr < SRAM_BASE_ADDR + SRAM_SIZE)) {
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writel(val, hdev->pcie_bar[SRAM_CFG_BAR_ID] +
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(addr - SRAM_BASE_ADDR));
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} else if (addr < DRAM_PHYS_BASE + hdev->asic_prop.dram_size) {
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u64 bar_base_addr = DRAM_PHYS_BASE +
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(addr & ~(prop->dram_pci_bar_size - 0x1ull));
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ddr_bar_addr = goya_set_ddr_bar_base(hdev, bar_base_addr);
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if (ddr_bar_addr != U64_MAX) {
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writel(val, hdev->pcie_bar[DDR_BAR_ID] +
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(addr - bar_base_addr));
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ddr_bar_addr = goya_set_ddr_bar_base(hdev,
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ddr_bar_addr);
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}
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if (ddr_bar_addr == U64_MAX)
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rc = -EIO;
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} else if (addr >= HOST_PHYS_BASE && addr < host_phys_end &&
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user_address && !iommu_present(&pci_bus_type)) {
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*(u32 *) phys_to_virt(addr - HOST_PHYS_BASE) = val;
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} else {
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rc = -EFAULT;
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}
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return rc;
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}
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static int goya_debugfs_read64(struct hl_device *hdev, u64 addr,
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bool user_address, u64 *val)
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{
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struct asic_fixed_properties *prop = &hdev->asic_prop;
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u64 ddr_bar_addr, host_phys_end;
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int rc = 0;
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host_phys_end = HOST_PHYS_BASE + HOST_PHYS_SIZE;
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if ((addr >= CFG_BASE) && (addr <= CFG_BASE + CFG_SIZE - sizeof(u64))) {
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u32 val_l = RREG32(addr - CFG_BASE);
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u32 val_h = RREG32(addr + sizeof(u32) - CFG_BASE);
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*val = (((u64) val_h) << 32) | val_l;
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} else if ((addr >= SRAM_BASE_ADDR) &&
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(addr <= SRAM_BASE_ADDR + SRAM_SIZE - sizeof(u64))) {
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*val = readq(hdev->pcie_bar[SRAM_CFG_BAR_ID] +
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(addr - SRAM_BASE_ADDR));
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} else if (addr <=
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DRAM_PHYS_BASE + hdev->asic_prop.dram_size - sizeof(u64)) {
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u64 bar_base_addr = DRAM_PHYS_BASE +
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(addr & ~(prop->dram_pci_bar_size - 0x1ull));
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ddr_bar_addr = goya_set_ddr_bar_base(hdev, bar_base_addr);
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if (ddr_bar_addr != U64_MAX) {
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*val = readq(hdev->pcie_bar[DDR_BAR_ID] +
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(addr - bar_base_addr));
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ddr_bar_addr = goya_set_ddr_bar_base(hdev,
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ddr_bar_addr);
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}
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if (ddr_bar_addr == U64_MAX)
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rc = -EIO;
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} else if (addr >= HOST_PHYS_BASE && addr < host_phys_end &&
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user_address && !iommu_present(&pci_bus_type)) {
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*val = *(u64 *) phys_to_virt(addr - HOST_PHYS_BASE);
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} else {
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rc = -EFAULT;
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}
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return rc;
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}
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static int goya_debugfs_write64(struct hl_device *hdev, u64 addr,
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bool user_address, u64 val)
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{
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struct asic_fixed_properties *prop = &hdev->asic_prop;
|
||||
u64 ddr_bar_addr, host_phys_end;
|
||||
int rc = 0;
|
||||
|
||||
host_phys_end = HOST_PHYS_BASE + HOST_PHYS_SIZE;
|
||||
|
||||
if ((addr >= CFG_BASE) && (addr <= CFG_BASE + CFG_SIZE - sizeof(u64))) {
|
||||
WREG32(addr - CFG_BASE, lower_32_bits(val));
|
||||
WREG32(addr + sizeof(u32) - CFG_BASE, upper_32_bits(val));
|
||||
|
||||
} else if ((addr >= SRAM_BASE_ADDR) &&
|
||||
(addr <= SRAM_BASE_ADDR + SRAM_SIZE - sizeof(u64))) {
|
||||
|
||||
writeq(val, hdev->pcie_bar[SRAM_CFG_BAR_ID] +
|
||||
(addr - SRAM_BASE_ADDR));
|
||||
|
||||
} else if (addr <=
|
||||
DRAM_PHYS_BASE + hdev->asic_prop.dram_size - sizeof(u64)) {
|
||||
|
||||
u64 bar_base_addr = DRAM_PHYS_BASE +
|
||||
(addr & ~(prop->dram_pci_bar_size - 0x1ull));
|
||||
|
||||
ddr_bar_addr = goya_set_ddr_bar_base(hdev, bar_base_addr);
|
||||
if (ddr_bar_addr != U64_MAX) {
|
||||
writeq(val, hdev->pcie_bar[DDR_BAR_ID] +
|
||||
(addr - bar_base_addr));
|
||||
|
||||
ddr_bar_addr = goya_set_ddr_bar_base(hdev,
|
||||
ddr_bar_addr);
|
||||
}
|
||||
if (ddr_bar_addr == U64_MAX)
|
||||
rc = -EIO;
|
||||
|
||||
} else if (addr >= HOST_PHYS_BASE && addr < host_phys_end &&
|
||||
user_address && !iommu_present(&pci_bus_type)) {
|
||||
*(u64 *) phys_to_virt(addr - HOST_PHYS_BASE) = val;
|
||||
|
||||
} else {
|
||||
rc = -EFAULT;
|
||||
}
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
static int goya_debugfs_read_dma(struct hl_device *hdev, u64 addr, u32 size,
|
||||
void *blob_addr)
|
||||
static int goya_debugfs_read_dma(struct hl_device *hdev, u64 addr, u32 size, void *blob_addr)
|
||||
{
|
||||
dev_err(hdev->dev, "Reading via DMA is unimplemented yet\n");
|
||||
return -EPERM;
|
||||
|
|
@ -5725,10 +5508,6 @@ static const struct hl_asic_funcs goya_funcs = {
|
|||
.update_eq_ci = goya_update_eq_ci,
|
||||
.context_switch = goya_context_switch,
|
||||
.restore_phase_topology = goya_restore_phase_topology,
|
||||
.debugfs_read32 = goya_debugfs_read32,
|
||||
.debugfs_write32 = goya_debugfs_write32,
|
||||
.debugfs_read64 = goya_debugfs_read64,
|
||||
.debugfs_write64 = goya_debugfs_write64,
|
||||
.debugfs_read_dma = goya_debugfs_read_dma,
|
||||
.add_device_attr = goya_add_device_attr,
|
||||
.handle_eqe = goya_handle_eqe,
|
||||
|
|
|
|||
Loading…
Reference in a new issue