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MIPS: BPF: Move register definition to the BPF header
The registers will be used by a subsequent patch introducing ASM helpers so move them to a common header. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: netdev@vger.kernel.org Cc: "David S. Miller" <davem@davemloft.net> Cc: Alexei Starovoitov <ast@plumgrid.com> Cc: Daniel Borkmann <dborkman@redhat.com> Cc: Hannes Frederic Sowa <hannes@stressinduktion.org> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/10528/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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2 changed files with 35 additions and 35 deletions
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@ -63,41 +63,6 @@
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#define ptr typeof(unsigned long)
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/* ABI specific return values */
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#ifdef CONFIG_32BIT /* O32 */
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#ifdef CONFIG_CPU_LITTLE_ENDIAN
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#define r_err MIPS_R_V1
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#define r_val MIPS_R_V0
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#else /* CONFIG_CPU_LITTLE_ENDIAN */
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#define r_err MIPS_R_V0
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#define r_val MIPS_R_V1
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#endif
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#else /* N64 */
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#define r_err MIPS_R_V0
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#define r_val MIPS_R_V0
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#endif
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#define r_ret MIPS_R_V0
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/*
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* Use 2 scratch registers to avoid pipeline interlocks.
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* There is no overhead during epilogue and prologue since
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* any of the $s0-$s6 registers will only be preserved if
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* they are going to actually be used.
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*/
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#define r_off MIPS_R_S2
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#define r_A MIPS_R_S3
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#define r_X MIPS_R_S4
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#define r_skb MIPS_R_S5
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#define r_M MIPS_R_S6
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#define r_s0 MIPS_R_T4 /* scratch reg 1 */
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#define r_s1 MIPS_R_T5 /* scratch reg 2 */
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#define r_tmp_imm MIPS_R_T6 /* No need to preserve this */
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#define r_tmp MIPS_R_T7 /* No need to preserve this */
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#define r_zero MIPS_R_ZERO
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#define r_sp MIPS_R_SP
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#define r_ra MIPS_R_RA
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#define SCRATCH_OFF(k) (4 * (k))
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/* JIT flags */
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@ -43,4 +43,39 @@
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#define MIPS_COND_X (0x1 << 5)
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#define MIPS_COND_K (0x1 << 6)
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/* ABI specific return values */
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#ifdef CONFIG_32BIT /* O32 */
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#ifdef CONFIG_CPU_LITTLE_ENDIAN
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#define r_err MIPS_R_V1
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#define r_val MIPS_R_V0
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#else /* CONFIG_CPU_LITTLE_ENDIAN */
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#define r_err MIPS_R_V0
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#define r_val MIPS_R_V1
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#endif
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#else /* N64 */
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#define r_err MIPS_R_V0
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#define r_val MIPS_R_V0
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#endif
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#define r_ret MIPS_R_V0
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/*
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* Use 2 scratch registers to avoid pipeline interlocks.
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* There is no overhead during epilogue and prologue since
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* any of the $s0-$s6 registers will only be preserved if
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* they are going to actually be used.
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*/
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#define r_off MIPS_R_S2
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#define r_A MIPS_R_S3
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#define r_X MIPS_R_S4
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#define r_skb MIPS_R_S5
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#define r_M MIPS_R_S6
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#define r_s0 MIPS_R_T4 /* scratch reg 1 */
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#define r_s1 MIPS_R_T5 /* scratch reg 2 */
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#define r_tmp_imm MIPS_R_T6 /* No need to preserve this */
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#define r_tmp MIPS_R_T7 /* No need to preserve this */
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#define r_zero MIPS_R_ZERO
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#define r_sp MIPS_R_SP
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#define r_ra MIPS_R_RA
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#endif /* BPF_JIT_MIPS_OP_H */
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