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MIPS: BPF: Move register definition to the BPF header

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The registers will be used by a subsequent patch introducing
ASM helpers so move them to a common header.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: netdev@vger.kernel.org
Cc: "David S. Miller" <davem@davemloft.net>
Cc: Alexei Starovoitov <ast@plumgrid.com>
Cc: Daniel Borkmann <dborkman@redhat.com>
Cc: Hannes Frederic Sowa <hannes@stressinduktion.org>
Cc: linux-kernel@vger.kernel.org
Cc: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/10528/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Markos Chandras 2015-06-04 11:56:14 +01:00 committed by Ralf Baechle
parent 5e0c5610ea
commit 79a8855c4a
2 changed files with 35 additions and 35 deletions
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35
arch/mips/net/bpf_jit.c
View file

@ -63,41 +63,6 @@
#define ptr typeof(unsigned long)
/* ABI specific return values */
#ifdef CONFIG_32BIT /* O32 */
#ifdef CONFIG_CPU_LITTLE_ENDIAN
#define r_err MIPS_R_V1
#define r_val MIPS_R_V0
#else /* CONFIG_CPU_LITTLE_ENDIAN */
#define r_err MIPS_R_V0
#define r_val MIPS_R_V1
#endif
#else /* N64 */
#define r_err MIPS_R_V0
#define r_val MIPS_R_V0
#endif
#define r_ret MIPS_R_V0
/*
* Use 2 scratch registers to avoid pipeline interlocks.
* There is no overhead during epilogue and prologue since
* any of the $s0-$s6 registers will only be preserved if
* they are going to actually be used.
*/
#define r_off MIPS_R_S2
#define r_A MIPS_R_S3
#define r_X MIPS_R_S4
#define r_skb MIPS_R_S5
#define r_M MIPS_R_S6
#define r_s0 MIPS_R_T4 /* scratch reg 1 */
#define r_s1 MIPS_R_T5 /* scratch reg 2 */
#define r_tmp_imm MIPS_R_T6 /* No need to preserve this */
#define r_tmp MIPS_R_T7 /* No need to preserve this */
#define r_zero MIPS_R_ZERO
#define r_sp MIPS_R_SP
#define r_ra MIPS_R_RA
#define SCRATCH_OFF(k) (4 * (k))
/* JIT flags */

35
arch/mips/net/bpf_jit.h
View file

@ -43,4 +43,39 @@
#define MIPS_COND_X (0x1 << 5)
#define MIPS_COND_K (0x1 << 6)
/* ABI specific return values */
#ifdef CONFIG_32BIT /* O32 */
#ifdef CONFIG_CPU_LITTLE_ENDIAN
#define r_err MIPS_R_V1
#define r_val MIPS_R_V0
#else /* CONFIG_CPU_LITTLE_ENDIAN */
#define r_err MIPS_R_V0
#define r_val MIPS_R_V1
#endif
#else /* N64 */
#define r_err MIPS_R_V0
#define r_val MIPS_R_V0
#endif
#define r_ret MIPS_R_V0
/*
* Use 2 scratch registers to avoid pipeline interlocks.
* There is no overhead during epilogue and prologue since
* any of the $s0-$s6 registers will only be preserved if
* they are going to actually be used.
*/
#define r_off MIPS_R_S2
#define r_A MIPS_R_S3
#define r_X MIPS_R_S4
#define r_skb MIPS_R_S5
#define r_M MIPS_R_S6
#define r_s0 MIPS_R_T4 /* scratch reg 1 */
#define r_s1 MIPS_R_T5 /* scratch reg 2 */
#define r_tmp_imm MIPS_R_T6 /* No need to preserve this */
#define r_tmp MIPS_R_T7 /* No need to preserve this */
#define r_zero MIPS_R_ZERO
#define r_sp MIPS_R_SP
#define r_ra MIPS_R_RA
#endif /* BPF_JIT_MIPS_OP_H */