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drm/i915/dg2: configure TRANS_DP2_CTL for DP 2.0
Set the DP 2.0 128b/132b channel encoding for UHBR rates. v2: Fix UHBR port clock check, use intel_dp_is_uhbr() Bspec: 54128 Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/c88b08d80a96d1229ae941b296590633be4d8711.1631191763.git.jani.nikula@intel.com
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1 changed files with 16 additions and 1 deletions
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@ -408,6 +408,20 @@ static u32 bdw_trans_port_sync_master_select(enum transcoder master_transcoder)
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return master_transcoder + 1;
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}
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static void
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intel_ddi_config_transcoder_dp2(struct intel_encoder *encoder,
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const struct intel_crtc_state *crtc_state)
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{
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struct drm_i915_private *i915 = to_i915(encoder->base.dev);
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enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
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u32 val = 0;
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if (intel_dp_is_uhbr(crtc_state))
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val = TRANS_DP2_128B132B_CHANNEL_CODING;
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intel_de_write(i915, TRANS_DP2_CTL(cpu_transcoder), val);
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}
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/*
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* Returns the TRANS_DDI_FUNC_CTL value based on CRTC state.
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*
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@ -2376,7 +2390,8 @@ static void dg2_ddi_pre_enable_dp(struct intel_atomic_state *state,
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*/
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intel_ddi_enable_pipe_clock(encoder, crtc_state);
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/* 5.b Not relevant to i915 for now */
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/* 5.b Configure transcoder for DP 2.0 128b/132b */
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intel_ddi_config_transcoder_dp2(encoder, crtc_state);
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/*
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* 5.c Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST
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