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drm/amd/display: fix 64bit division issue on 32bit OS
Replace "/" with div_u64 for 64bit division on 32bit OS. Signed-off-by: Lang Yu <Lang.Yu@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Acked-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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3 changed files with 5 additions and 4 deletions
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@ -3688,8 +3688,8 @@ uint32_t dc_link_bandwidth_kbps(
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* but the difference is minimal and is in a safe direction,
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* which all works well around potential ambiguity of DP 1.4a spec.
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*/
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link_bw_kbps = mul_u64_u32_shr(BIT_ULL(32) * 970LL / 1000,
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link_bw_kbps, 32);
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long long fec_link_bw_kbps = link_bw_kbps * 970LL;
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link_bw_kbps = (uint32_t)(div64_s64(fec_link_bw_kbps, 1000LL));
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}
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return link_bw_kbps;
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@ -240,7 +240,7 @@ static bool calc_fb_divider_checking_tolerance(
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pll_settings->calculated_pix_clk_100hz =
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actual_calculated_clock_100hz;
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pll_settings->vco_freq =
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actual_calculated_clock_100hz * post_divider / 10;
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div_u64(actual_calculated_clock_100hz * post_divider, 10);
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return true;
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}
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return false;
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@ -3506,7 +3506,8 @@ void dcn20_update_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_s
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calculated_states[i].dram_speed_mts = uclk_states[i] * 16 / 1000;
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// FCLK:UCLK ratio is 1.08
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min_fclk_required_by_uclk = mul_u64_u32_shr(BIT_ULL(32) * 1080 / 1000000, uclk_states[i], 32);
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min_fclk_required_by_uclk = div_u64(((unsigned long long)uclk_states[i]) * 1080,
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1000000);
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calculated_states[i].fabricclk_mhz = (min_fclk_required_by_uclk < min_dcfclk) ?
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min_dcfclk : min_fclk_required_by_uclk;
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