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A few more macros to access MIPS R2 architecture registers.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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1 changed files with 28 additions and 0 deletions
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@ -95,6 +95,16 @@
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#define CP0_S1_DERRADDR1 $27
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#define CP0_S1_INTCONTROL $20
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/*
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* Coprocessor 0 Set 2 register names
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*/
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#define CP0_S2_SRSCTL $12 /* MIPSR2 */
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/*
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* Coprocessor 0 Set 3 register names
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*/
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#define CP0_S3_SRSMAP $12 /* MIPSR2 */
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/*
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* TX39 Series
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*/
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@ -984,6 +994,22 @@ do { \
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#define read_c0_errorepc() __read_ulong_c0_register($30, 0)
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#define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val)
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/* MIPSR2 */
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#define read_c0_hwrena() __read_32bit_c0_register($7,0)
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#define write_c0_hwrena(val) __write_32bit_c0_register($7, 0, val)
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#define read_c0_intctl() __read_32bit_c0_register($12, 1)
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#define write_c0_intctl(val) __write_32bit_c0_register($12, 1, val)
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#define read_c0_srsctl() __read_32bit_c0_register($12, 2)
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#define write_c0_srsctl(val) __write_32bit_c0_register($12, 2, val)
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#define read_c0_srsmap() __read_32bit_c0_register($12, 3)
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#define write_c0_srsmap(val) __write_32bit_c0_register($12, 3, val)
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#define read_c0_ebase() __read_32bit_c0_register($15,1)
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#define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val)
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/*
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* Macros to access the floating point coprocessor control registers
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*/
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@ -1357,6 +1383,8 @@ __BUILD_SET_C0(status)
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__BUILD_SET_C0(cause)
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__BUILD_SET_C0(config)
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__BUILD_SET_C0(intcontrol)
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__BUILD_SET_C0(intctl)
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__BUILD_SET_C0(srsmap)
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#endif /* !__ASSEMBLY__ */
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