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synced 2024-10-02 15:18:19 +00:00
drm/amdgpu: Use mask for active clusters
Use a mask of available active clusters instead of using only the number of active clusters. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
parent
bbca579fd2
commit
7a1efad04c
4 changed files with 49 additions and 28 deletions
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@ -1070,7 +1070,8 @@ struct amdgpu_device {
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bool job_hang;
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bool dc_enabled;
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uint32_t num_aid;
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/* Mask of active clusters */
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uint32_t aid_mask;
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};
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static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev)
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@ -358,25 +358,26 @@ static int aqua_vanjaram_xcp_mgr_init(struct amdgpu_device *adev)
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int aqua_vanjaram_init_soc_config(struct amdgpu_device *adev)
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{
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u32 inst_mask = adev->sdma.sdma_mask;
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int ret;
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int ret, i, num_inst;
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/* generally 1 AID supports 4 instances */
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adev->sdma.num_inst_per_aid = 4;
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adev->sdma.num_instances = NUM_SDMA(adev->sdma.sdma_mask);
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adev->num_aid = 1;
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adev->aid_mask = i = 1;
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inst_mask >>= adev->sdma.num_inst_per_aid;
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for (const u32 mask = (1 << adev->sdma.num_inst_per_aid) - 1; inst_mask;
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inst_mask >>= adev->sdma.num_inst_per_aid) {
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inst_mask >>= adev->sdma.num_inst_per_aid, ++i) {
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if ((inst_mask & mask) == mask)
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adev->num_aid++;
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adev->aid_mask |= (1 << i);
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}
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num_inst = hweight32(adev->aid_mask);
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adev->vcn.num_inst_per_aid = 1;
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adev->vcn.num_vcn_inst = adev->vcn.num_inst_per_aid * adev->num_aid;
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adev->vcn.num_vcn_inst = adev->vcn.num_inst_per_aid * num_inst;
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adev->jpeg.num_inst_per_aid = 1;
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adev->jpeg.num_jpeg_inst = adev->jpeg.num_inst_per_aid * adev->num_aid;
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adev->jpeg.num_jpeg_inst = adev->jpeg.num_inst_per_aid * num_inst;
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ret = aqua_vanjaram_xcp_mgr_init(adev);
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if (ret)
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@ -1674,6 +1674,7 @@ static int gmc_v9_0_sw_init(void *handle)
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{
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int r, vram_width = 0, vram_type = 0, vram_vendor = 0, dma_addr_bits;
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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unsigned long inst_mask = adev->aid_mask;
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adev->gfxhub.funcs->init(adev);
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@ -1757,7 +1758,9 @@ static int gmc_v9_0_sw_init(void *handle)
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case IP_VERSION(9, 4, 3):
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bitmap_set(adev->vmhubs_mask, AMDGPU_GFXHUB(0),
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NUM_XCC(adev->gfx.xcc_mask));
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bitmap_set(adev->vmhubs_mask, AMDGPU_MMHUB0(0), adev->num_aid);
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inst_mask <<= AMDGPU_MMHUB0(0);
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bitmap_or(adev->vmhubs_mask, adev->vmhubs_mask, &inst_mask, 32);
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amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
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break;
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@ -54,9 +54,11 @@ static void mmhub_v1_8_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmi
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uint64_t page_table_base)
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{
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struct amdgpu_vmhub *hub;
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u32 inst_mask;
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int i;
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for (i = 0; i < adev->num_aid; i++) {
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inst_mask = adev->aid_mask;
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for_each_inst(i, inst_mask) {
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hub = &adev->vmhub[AMDGPU_MMHUB0(i)];
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WREG32_SOC15_OFFSET(MMHUB, i,
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regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
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@ -73,6 +75,7 @@ static void mmhub_v1_8_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmi
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static void mmhub_v1_8_init_gart_aperture_regs(struct amdgpu_device *adev)
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{
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uint64_t pt_base;
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u32 inst_mask;
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int i;
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if (adev->gmc.pdb0_bo)
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@ -85,7 +88,8 @@ static void mmhub_v1_8_init_gart_aperture_regs(struct amdgpu_device *adev)
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/* If use GART for FB translation, vmid0 page table covers both
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* vram and system memory (gart)
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*/
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for (i = 0; i < adev->num_aid; i++) {
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inst_mask = adev->aid_mask;
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for_each_inst(i, inst_mask) {
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if (adev->gmc.pdb0_bo) {
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WREG32_SOC15(MMHUB, i,
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regVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
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@ -121,11 +125,12 @@ static void mmhub_v1_8_init_gart_aperture_regs(struct amdgpu_device *adev)
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static void mmhub_v1_8_init_system_aperture_regs(struct amdgpu_device *adev)
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{
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uint32_t tmp, inst_mask;
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uint64_t value;
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uint32_t tmp;
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int i;
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for (i = 0; i < adev->num_aid; i++) {
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inst_mask = adev->aid_mask;
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for_each_inst(i, inst_mask) {
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/* Program the AGP BAR */
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WREG32_SOC15(MMHUB, i, regMC_VM_AGP_BASE, 0);
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WREG32_SOC15(MMHUB, i, regMC_VM_AGP_BOT,
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@ -183,11 +188,12 @@ static void mmhub_v1_8_init_system_aperture_regs(struct amdgpu_device *adev)
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static void mmhub_v1_8_init_tlb_regs(struct amdgpu_device *adev)
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{
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uint32_t tmp;
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uint32_t tmp, inst_mask;
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int i;
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/* Setup TLB control */
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for (i = 0; i < adev->num_aid; i++) {
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inst_mask = adev->aid_mask;
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for_each_inst(i, inst_mask) {
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tmp = RREG32_SOC15(MMHUB, i, regMC_VM_MX_L1_TLB_CNTL);
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tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB,
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@ -208,14 +214,15 @@ static void mmhub_v1_8_init_tlb_regs(struct amdgpu_device *adev)
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static void mmhub_v1_8_init_cache_regs(struct amdgpu_device *adev)
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{
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uint32_t tmp;
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uint32_t tmp, inst_mask;
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int i;
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if (amdgpu_sriov_vf(adev))
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return;
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/* Setup L2 cache */
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for (i = 0; i < adev->num_aid; i++) {
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inst_mask = adev->aid_mask;
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for_each_inst(i, inst_mask) {
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tmp = RREG32_SOC15(MMHUB, i, regVM_L2_CNTL);
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tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
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tmp = REG_SET_FIELD(tmp, VM_L2_CNTL,
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@ -267,10 +274,11 @@ static void mmhub_v1_8_init_cache_regs(struct amdgpu_device *adev)
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static void mmhub_v1_8_enable_system_domain(struct amdgpu_device *adev)
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{
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uint32_t tmp;
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uint32_t tmp, inst_mask;
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int i;
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for (i = 0; i < adev->num_aid; i++) {
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inst_mask = adev->aid_mask;
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for_each_inst(i, inst_mask) {
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tmp = RREG32_SOC15(MMHUB, i, regVM_CONTEXT0_CNTL);
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tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
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tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH,
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@ -286,12 +294,14 @@ static void mmhub_v1_8_enable_system_domain(struct amdgpu_device *adev)
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static void mmhub_v1_8_disable_identity_aperture(struct amdgpu_device *adev)
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{
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u32 inst_mask;
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int i;
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if (amdgpu_sriov_vf(adev))
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return;
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for (i = 0; i < adev->num_aid; i++) {
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inst_mask = adev->aid_mask;
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for_each_inst(i, inst_mask) {
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WREG32_SOC15(MMHUB, i,
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regVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,
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0XFFFFFFFF);
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@ -317,7 +327,7 @@ static void mmhub_v1_8_setup_vmid_config(struct amdgpu_device *adev)
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{
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struct amdgpu_vmhub *hub;
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unsigned num_level, block_size;
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uint32_t tmp;
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uint32_t tmp, inst_mask;
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int i, j;
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num_level = adev->vm_manager.num_level;
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@ -327,7 +337,8 @@ static void mmhub_v1_8_setup_vmid_config(struct amdgpu_device *adev)
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else
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block_size -= 9;
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for (j = 0; j < adev->num_aid; j++) {
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inst_mask = adev->aid_mask;
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for_each_inst(j, inst_mask) {
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hub = &adev->vmhub[AMDGPU_MMHUB0(j)];
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for (i = 0; i <= 14; i++) {
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tmp = RREG32_SOC15_OFFSET(MMHUB, j, regVM_CONTEXT1_CNTL,
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@ -382,9 +393,10 @@ static void mmhub_v1_8_setup_vmid_config(struct amdgpu_device *adev)
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static void mmhub_v1_8_program_invalidation(struct amdgpu_device *adev)
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{
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struct amdgpu_vmhub *hub;
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unsigned i, j;
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u32 i, j, inst_mask;
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for (j = 0; j < adev->num_aid; j++) {
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inst_mask = adev->aid_mask;
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for_each_inst(j, inst_mask) {
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hub = &adev->vmhub[AMDGPU_MMHUB0(j)];
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for (i = 0; i < 18; ++i) {
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WREG32_SOC15_OFFSET(MMHUB, j,
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@ -429,10 +441,11 @@ static void mmhub_v1_8_gart_disable(struct amdgpu_device *adev)
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{
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struct amdgpu_vmhub *hub;
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u32 tmp;
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u32 i, j;
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u32 i, j, inst_mask;
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/* Disable all tables */
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for (j = 0; j < adev->num_aid; j++) {
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inst_mask = adev->aid_mask;
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for_each_inst(j, inst_mask) {
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hub = &adev->vmhub[AMDGPU_MMHUB0(j)];
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for (i = 0; i < 16; i++)
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WREG32_SOC15_OFFSET(MMHUB, j, regVM_CONTEXT0_CNTL,
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@ -465,13 +478,14 @@ static void mmhub_v1_8_gart_disable(struct amdgpu_device *adev)
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*/
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static void mmhub_v1_8_set_fault_enable_default(struct amdgpu_device *adev, bool value)
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{
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u32 tmp;
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u32 tmp, inst_mask;
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int i;
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if (amdgpu_sriov_vf(adev))
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return;
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for (i = 0; i < adev->num_aid; i++) {
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inst_mask = adev->aid_mask;
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for_each_inst(i, inst_mask) {
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tmp = RREG32_SOC15(MMHUB, i, regVM_L2_PROTECTION_FAULT_CNTL);
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tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
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RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
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@ -510,9 +524,11 @@ static void mmhub_v1_8_set_fault_enable_default(struct amdgpu_device *adev, bool
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static void mmhub_v1_8_init(struct amdgpu_device *adev)
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{
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struct amdgpu_vmhub *hub;
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u32 inst_mask;
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int i;
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for (i = 0; i < adev->num_aid; i++) {
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inst_mask = adev->aid_mask;
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for_each_inst(i, inst_mask) {
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hub = &adev->vmhub[AMDGPU_MMHUB0(i)];
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hub->ctx0_ptb_addr_lo32 = SOC15_REG_OFFSET(MMHUB, i,
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