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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-27 19:29:37 +00:00
drm/amdgpu: Update SMC/DPM for Stoney
Stoney is SMC 8.x. Signed-off-by: Samuel Li <samuel.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
parent
aade2f04f9
commit
7a753c3f34
2 changed files with 65 additions and 16 deletions
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@ -1262,6 +1262,7 @@ static void cz_apply_state_adjust_rules(struct amdgpu_device *adev,
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static int cz_dpm_enable(struct amdgpu_device *adev)
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{
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const char *chip_name;
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int ret = 0;
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/* renable will hang up SMU, so check first */
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@ -1270,21 +1271,33 @@ static int cz_dpm_enable(struct amdgpu_device *adev)
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cz_program_voting_clients(adev);
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switch (adev->asic_type) {
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case CHIP_CARRIZO:
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chip_name = "carrizo";
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break;
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case CHIP_STONEY:
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chip_name = "stoney";
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break;
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default:
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BUG();
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}
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ret = cz_start_dpm(adev);
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if (ret) {
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DRM_ERROR("Carrizo DPM enable failed\n");
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DRM_ERROR("%s DPM enable failed\n", chip_name);
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return -EINVAL;
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}
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ret = cz_program_bootup_state(adev);
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if (ret) {
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DRM_ERROR("Carrizo bootup state program failed\n");
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DRM_ERROR("%s bootup state program failed\n", chip_name);
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return -EINVAL;
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}
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ret = cz_enable_didt(adev, true);
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if (ret) {
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DRM_ERROR("Carrizo enable di/dt failed\n");
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DRM_ERROR("%s enable di/dt failed\n", chip_name);
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return -EINVAL;
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}
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@ -1351,7 +1364,7 @@ static int cz_dpm_disable(struct amdgpu_device *adev)
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ret = cz_enable_didt(adev, false);
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if (ret) {
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DRM_ERROR("Carrizo disable di/dt failed\n");
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DRM_ERROR("disable di/dt failed\n");
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return -EINVAL;
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}
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@ -312,13 +312,16 @@ int cz_smu_start(struct amdgpu_device *adev)
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UCODE_ID_CP_MEC_JT1_MASK |
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UCODE_ID_CP_MEC_JT2_MASK;
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if (adev->asic_type == CHIP_STONEY)
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fw_to_check &= ~(UCODE_ID_SDMA1_MASK | UCODE_ID_CP_MEC_JT2_MASK);
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cz_smu_request_load_fw(adev);
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ret = cz_smu_check_fw_load_finish(adev, fw_to_check);
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if (ret)
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return ret;
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/* manually load MEC firmware for CZ */
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if (adev->asic_type == CHIP_CARRIZO) {
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if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY) {
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ret = cz_load_mec_firmware(adev);
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if (ret) {
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dev_err(adev->dev, "(%d) Mec Firmware load failed\n", ret);
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@ -336,6 +339,9 @@ int cz_smu_start(struct amdgpu_device *adev)
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AMDGPU_CPMEC2_UCODE_LOADED |
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AMDGPU_CPRLC_UCODE_LOADED;
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if (adev->asic_type == CHIP_STONEY)
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adev->smu.fw_flags &= ~(AMDGPU_SDMA1_UCODE_LOADED | AMDGPU_CPMEC2_UCODE_LOADED);
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return ret;
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}
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@ -601,8 +607,13 @@ static int cz_smu_construct_toc_for_vddgfx_exit(struct amdgpu_device *adev)
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CZ_SCRATCH_ENTRY_UCODE_ID_CP_ME, false);
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cz_smu_populate_single_ucode_load_task(adev,
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CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1, false);
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cz_smu_populate_single_ucode_load_task(adev,
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if (adev->asic_type == CHIP_STONEY) {
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cz_smu_populate_single_ucode_load_task(adev,
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CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1, false);
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} else {
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cz_smu_populate_single_ucode_load_task(adev,
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CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT2, false);
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}
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cz_smu_populate_single_ucode_load_task(adev,
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CZ_SCRATCH_ENTRY_UCODE_ID_RLC_G, false);
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}
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@ -642,8 +653,13 @@ static int cz_smu_construct_toc_for_bootup(struct amdgpu_device *adev)
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if (adev->firmware.smu_load) {
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cz_smu_populate_single_ucode_load_task(adev,
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CZ_SCRATCH_ENTRY_UCODE_ID_SDMA0, false);
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cz_smu_populate_single_ucode_load_task(adev,
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if (adev->asic_type == CHIP_STONEY) {
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cz_smu_populate_single_ucode_load_task(adev,
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CZ_SCRATCH_ENTRY_UCODE_ID_SDMA0, false);
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} else {
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cz_smu_populate_single_ucode_load_task(adev,
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CZ_SCRATCH_ENTRY_UCODE_ID_SDMA1, false);
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}
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cz_smu_populate_single_ucode_load_task(adev,
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CZ_SCRATCH_ENTRY_UCODE_ID_CP_CE, false);
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cz_smu_populate_single_ucode_load_task(adev,
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@ -652,8 +668,13 @@ static int cz_smu_construct_toc_for_bootup(struct amdgpu_device *adev)
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CZ_SCRATCH_ENTRY_UCODE_ID_CP_ME, false);
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cz_smu_populate_single_ucode_load_task(adev,
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CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1, false);
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cz_smu_populate_single_ucode_load_task(adev,
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if (adev->asic_type == CHIP_STONEY) {
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cz_smu_populate_single_ucode_load_task(adev,
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CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1, false);
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} else {
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cz_smu_populate_single_ucode_load_task(adev,
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CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT2, false);
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}
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cz_smu_populate_single_ucode_load_task(adev,
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CZ_SCRATCH_ENTRY_UCODE_ID_RLC_G, true);
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}
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@ -888,10 +909,18 @@ int cz_smu_init(struct amdgpu_device *adev)
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CZ_SCRATCH_ENTRY_UCODE_ID_SDMA0,
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&priv->driver_buffer[priv->driver_buffer_length++]))
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goto smu_init_failed;
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if (cz_smu_populate_single_firmware_entry(adev,
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CZ_SCRATCH_ENTRY_UCODE_ID_SDMA1,
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&priv->driver_buffer[priv->driver_buffer_length++]))
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goto smu_init_failed;
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if (adev->asic_type == CHIP_STONEY) {
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if (cz_smu_populate_single_firmware_entry(adev,
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CZ_SCRATCH_ENTRY_UCODE_ID_SDMA0,
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&priv->driver_buffer[priv->driver_buffer_length++]))
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goto smu_init_failed;
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} else {
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if (cz_smu_populate_single_firmware_entry(adev,
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CZ_SCRATCH_ENTRY_UCODE_ID_SDMA1,
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&priv->driver_buffer[priv->driver_buffer_length++]))
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goto smu_init_failed;
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}
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if (cz_smu_populate_single_firmware_entry(adev,
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CZ_SCRATCH_ENTRY_UCODE_ID_CP_CE,
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&priv->driver_buffer[priv->driver_buffer_length++]))
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@ -908,10 +937,17 @@ int cz_smu_init(struct amdgpu_device *adev)
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CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1,
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&priv->driver_buffer[priv->driver_buffer_length++]))
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goto smu_init_failed;
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if (cz_smu_populate_single_firmware_entry(adev,
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CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT2,
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&priv->driver_buffer[priv->driver_buffer_length++]))
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goto smu_init_failed;
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if (adev->asic_type == CHIP_STONEY) {
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if (cz_smu_populate_single_firmware_entry(adev,
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CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1,
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&priv->driver_buffer[priv->driver_buffer_length++]))
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goto smu_init_failed;
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} else {
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if (cz_smu_populate_single_firmware_entry(adev,
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CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT2,
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&priv->driver_buffer[priv->driver_buffer_length++]))
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goto smu_init_failed;
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}
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if (cz_smu_populate_single_firmware_entry(adev,
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CZ_SCRATCH_ENTRY_UCODE_ID_RLC_G,
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&priv->driver_buffer[priv->driver_buffer_length++]))
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