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Merge tag 'imx-dt-4.17' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/dt

Browse source 
Pull "i.MX device tree updates for 4.17" from Shawn Guo:

 - New board support: phyBOARD-Mira i.MX6 boards; Advantech DMS-BA16
   i.MX6Q board; Toradex Colibri iMX6ULL boards.
 - ZII RDU board updates: add RAVE SP device; disable on-chip watchdog
   as the external watchdog is being used instead; improve USDHC node
   regarding to voltage and SDIO capability.
 - i.MX6UL/ULL updates: cpufreq clock cleanup; add IOMUXC_SNVS pins and
   missing daisy chain configurations; add more devices like WDOG3,
   UART8, PMU, architected timer etc.
 - Hummingboard updates: correct USBOTG-ID pin; remove mention of
   nonexistent node.
 - Fix compatibles of atmel eeprom devices.
 - A couple of improvements on i.MX25 pinfunc header regarding to eSDHC
   pins.
 - A bunch of patches from Fabio and Marco to fix DTC warnings seen with
   W=1 switch.
 - Remove GPU subsystem nodes, as they are not needed by the etnaviv
   driver anymore and have been removed from the binding.
 - Add FIFO depth definition for i.MX25 SSI devices.
 - Add missing '#sound-dai-cells' for sgtl5000 codec which is complained
   by DTC.
 - Miscellaneous and random updates.

* tag 'imx-dt-4.17' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (66 commits)
  ARM: dts: i.MX25: define SSI FIFO depth
  ARM: dts: vf610m4: Remove the zero length reg property
  ARM: dts: vf610m4: Remove skeleton.dtsi inclusion
  ARM: dts: vf500: Remove the zero length reg property
  ARM: dts: vf: Add memory node unit name
  ARM: dts: vf500: Remove skeleton.dtsi inclusion
  ARM: dts: imx7s: add temperature monitor support
  ARM: dts: imx: Add missing #sound-dai-cells for sgtl5000 codec
  ARM: dts: imx51-zii-rdu1: Add node for RAVE SP device
  ARM: dts: imx6: RDU2: Add RAVE SP device
  ARM: dts: imx5: Pass the memory unit-address
  ARM: dts: imx7s: add spba-bus abstraction
  ARM: dts: imx6dl-icore-rqs: Fix invalid PHY address assignment for ethernet
  ARM: dts: imx6ul: add wdog3 node
  ARM: dts: imx7: add CPU PMU support
  ARM: dts: imx6dl-colibri-eval-v3: Add chosen node
  ARM: dts: imx6: Pass memory unit-adress
  ARM: dts: imx6dl: remove 'lcdif' node
  ARM: dts: hummingboard: Remove mention of nonexistent node
  ARM: dts: imx6qdl-hummingboard: fix USBOTG-ID pin
  ...
This commit is contained in:
Arnd Bergmann 2018-03-15 16:06:55 +01:00
commit 7a76aad026
201 changed files with 3312 additions and 998 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

9
arch/arm/boot/dts/Makefile
View file

@ -401,6 +401,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6dl-icore-rqs.dtb \
imx6dl-nit6xlite.dtb \
imx6dl-nitrogen6x.dtb \
imx6dl-phytec-mira-rdk-nand.dtb \
imx6dl-phytec-pbab01.dtb \
imx6dl-rex-basic.dtb \
imx6dl-riotboard.dtb \
@ -440,6 +441,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6q-dfi-fs700-m60.dtb \
imx6q-display5-tianma-tm070-1280x768.dtb \
imx6q-dmo-edmqmx6.dtb \
imx6q-dms-ba16.dtb \
imx6q-evi.dtb \
imx6q-gk802.dtb \
imx6q-gw51xx.dtb \
@ -470,6 +472,8 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6q-nitrogen6_max.dtb \
imx6q-nitrogen6_som2.dtb \
imx6q-novena.dtb \
imx6q-phytec-mira-rdk-emmc.dtb \
imx6q-phytec-mira-rdk-nand.dtb \
imx6q-phytec-pbab01.dtb \
imx6q-pistachio.dtb \
imx6q-rex-pro.dtb \
@ -499,6 +503,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6q-zii-rdu2.dtb \
imx6qp-nitrogen6_max.dtb \
imx6qp-nitrogen6_som2.dtb \
imx6qp-phytec-mira-rdk-nand.dtb \
imx6qp-sabreauto.dtb \
imx6qp-sabresd.dtb \
imx6qp-tx6qp-8037.dtb \
@ -531,7 +536,9 @@ dtb-$(CONFIG_SOC_IMX6UL) += \
imx6ul-tx6ul-0010.dtb \
imx6ul-tx6ul-0011.dtb \
imx6ul-tx6ul-mainboard.dtb \
imx6ull-14x14-evk.dtb
imx6ull-14x14-evk.dtb \
imx6ull-colibri-eval-v3.dtb \
imx6ull-colibri-wifi-eval-v3.dtb
dtb-$(CONFIG_SOC_IMX7D) += \
imx7d-cl-som-imx7.dtb \
imx7d-colibri-emmc-eval-v3.dtb \

2
arch/arm/boot/dts/imx1-ads.dts
View file

@ -20,7 +20,7 @@ chosen {
stdout-path = &uart1;
};
memory {
memory@8000000 {
reg = <0x08000000 0x04000000>;
};

2
arch/arm/boot/dts/imx1-apf9328.dts
View file

@ -20,7 +20,7 @@ chosen {
stdout-path = &uart1;
};
memory {
memory@8000000 {
reg = <0x08000000 0x00800000>;
};
};

2
arch/arm/boot/dts/imx1.dtsi
View file

@ -25,7 +25,7 @@ / {
* Also for U-Boot there must be a pre-existing /memory node.
*/
chosen {};
memory { device_type = "memory"; reg = <0 0>; };
memory { device_type = "memory"; };
aliases {
gpio0 = &gpio1;

2
arch/arm/boot/dts/imx23-evk.dts
View file

@ -16,7 +16,7 @@ / {
model = "Freescale i.MX23 Evaluation Kit";
compatible = "fsl,imx23-evk", "fsl,imx23";
memory {
memory@40000000 {
reg = <0x40000000 0x08000000>;
};

2
arch/arm/boot/dts/imx23-olinuxino.dts
View file

@ -19,7 +19,7 @@ / {
model = "i.MX23 Olinuxino Low Cost Board";
compatible = "olimex,imx23-olinuxino", "fsl,imx23";
memory {
memory@40000000 {
reg = <0x40000000 0x04000000>;
};

2
arch/arm/boot/dts/imx23-sansa.dts
View file

@ -49,7 +49,7 @@ / {
model = "SanDisk Sansa Fuze+";
compatible = "sandisk,sansa_fuze_plus", "fsl,imx23";
memory {
memory@40000000 {
reg = <0x40000000 0x04000000>;
};

2
arch/arm/boot/dts/imx23-stmp378x_devb.dts
View file

@ -16,7 +16,7 @@ / {
model = "Freescale STMP378x Development Board";
compatible = "fsl,stmp378x-devb", "fsl,imx23";
memory {
memory@40000000 {
reg = <0x40000000 0x04000000>;
};

2
arch/arm/boot/dts/imx23-xfi3.dts
View file

@ -48,7 +48,7 @@ / {
model = "Creative ZEN X-Fi3";
compatible = "creative,x-fi3", "fsl,imx23";
memory {
memory@40000000 {
reg = <0x40000000 0x04000000>;
};

8
arch/arm/boot/dts/imx23.dtsi
View file

@ -23,7 +23,7 @@ / {
* Also for U-Boot there must be a pre-existing /memory node.
*/
chosen {};
memory { device_type = "memory"; reg = <0 0>; };
memory { device_type = "memory"; };
aliases {
gpio0 = &gpio0;
@ -222,7 +222,8 @@ MX23_PAD_GPMI_CE0N__GPMI_CE0N
fsl,pull-up = <MXS_PULL_DISABLE>;
};
gpmi_pins_fixup: gpmi-pins-fixup {
gpmi_pins_fixup: gpmi-pins-fixup@0 {
reg = <0>;
fsl,pinmux-ids = <
MX23_PAD_GPMI_WPN__GPMI_WPN
MX23_PAD_GPMI_WRN__GPMI_WRN
@ -266,7 +267,8 @@ MX23_PAD_SSP1_SCK__SSP1_SCK
fsl,pull-up = <MXS_PULL_ENABLE>;
};
mmc0_pins_fixup: mmc0-pins-fixup {
mmc0_pins_fixup: mmc0-pins-fixup@0 {
reg = <0>;
fsl,pinmux-ids = <
MX23_PAD_SSP1_DETECT__SSP1_DETECT
MX23_PAD_SSP1_SCK__SSP1_SCK

2
arch/arm/boot/dts/imx25-eukrea-cpuimx25.dtsi
View file

@ -17,7 +17,7 @@ / {
model = "Eukrea CPUIMX25";
compatible = "eukrea,cpuimx25", "fsl,imx25";
memory {
memory@80000000 {
reg = <0x80000000 0x4000000>; /* 64M */
};
};

12
arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts
View file

@ -88,12 +88,12 @@ MX25_PAD_KPP_COL0__AUD5_TXD 0xe0
pinctrl_esdhc1: esdhc1grp {
fsl,pins = <
MX25_PAD_SD1_CMD__SD1_CMD 0x400000c0
MX25_PAD_SD1_CLK__SD1_CLK 0x400000c0
MX25_PAD_SD1_DATA0__SD1_DATA0 0x400000c0
MX25_PAD_SD1_DATA1__SD1_DATA1 0x400000c0
MX25_PAD_SD1_DATA2__SD1_DATA2 0x400000c0
MX25_PAD_SD1_DATA3__SD1_DATA3 0x400000c0
MX25_PAD_SD1_CMD__ESDHC1_CMD 0x400000c0
MX25_PAD_SD1_CLK__ESDHC1_CLK 0x400000c0
MX25_PAD_SD1_DATA0__ESDHC1_DAT0 0x400000c0
MX25_PAD_SD1_DATA1__ESDHC1_DAT1 0x400000c0
MX25_PAD_SD1_DATA2__ESDHC1_DAT2 0x400000c0
MX25_PAD_SD1_DATA3__ESDHC1_DAT3 0x400000c0
>;
};

2
arch/arm/boot/dts/imx25-karo-tx25.dts
View file

@ -36,7 +36,7 @@ reg_fec_phy: regulator@0 {
};
};
memory {
memory@80000000 {
reg = <0x80000000 0x02000000 0x90000000 0x02000000>;
};
};

14
arch/arm/boot/dts/imx25-pdk.dts
View file

@ -18,7 +18,7 @@ / {
model = "Freescale i.MX25 Product Development Kit";
compatible = "fsl,imx25-pdk", "fsl,imx25";
memory {
memory@80000000 {
reg = <0x80000000 0x4000000>;
};
@ -165,12 +165,12 @@ MX25_PAD_D14__GPIO_4_6 0x80000000
pinctrl_esdhc1: esdhc1grp {
fsl,pins = <
MX25_PAD_SD1_CMD__SD1_CMD 0x80000000
MX25_PAD_SD1_CLK__SD1_CLK 0x80000000
MX25_PAD_SD1_DATA0__SD1_DATA0 0x80000000
MX25_PAD_SD1_DATA1__SD1_DATA1 0x80000000
MX25_PAD_SD1_DATA2__SD1_DATA2 0x80000000
MX25_PAD_SD1_DATA3__SD1_DATA3 0x80000000
MX25_PAD_SD1_CMD__ESDHC1_CMD 0x80000000
MX25_PAD_SD1_CLK__ESDHC1_CLK 0x80000000
MX25_PAD_SD1_DATA0__ESDHC1_DAT0 0x80000000
MX25_PAD_SD1_DATA1__ESDHC1_DAT1 0x80000000
MX25_PAD_SD1_DATA2__ESDHC1_DAT2 0x80000000
MX25_PAD_SD1_DATA3__ESDHC1_DAT3 0x80000000
MX25_PAD_A14__GPIO_2_0 0x80000000
MX25_PAD_A15__GPIO_2_1 0x80000000
>;

72
arch/arm/boot/dts/imx25-pinfunc.h
View file

@ -151,21 +151,21 @@
#define MX25_PAD_D15__D15 0x088 0x280 0x000 0x00 0x000
#define MX25_PAD_D15__LD16 0x088 0x280 0x000 0x01 0x000
#define MX25_PAD_D15__GPIO_4_5 0x088 0x280 0x000 0x05 0x000
#define MX25_PAD_D15__SDHC1_DAT7 0x088 0x280 0x4d8 0x06 0x000
#define MX25_PAD_D15__ESDHC1_DAT7 0x088 0x280 0x4d8 0x06 0x000
#define MX25_PAD_D14__D14 0x08c 0x284 0x000 0x00 0x000
#define MX25_PAD_D14__LD17 0x08c 0x284 0x000 0x01 0x000
#define MX25_PAD_D14__GPIO_4_6 0x08c 0x284 0x000 0x05 0x000
#define MX25_PAD_D14__SDHC1_DAT6 0x08c 0x284 0x4d4 0x06 0x000
#define MX25_PAD_D14__ESDHC1_DAT6 0x08c 0x284 0x4d4 0x06 0x000
#define MX25_PAD_D13__D13 0x090 0x288 0x000 0x00 0x000
#define MX25_PAD_D13__LD18 0x090 0x288 0x000 0x01 0x000
#define MX25_PAD_D13__GPIO_4_7 0x090 0x288 0x000 0x05 0x000
#define MX25_PAD_D13__SDHC1_DAT5 0x090 0x288 0x4d0 0x06 0x000
#define MX25_PAD_D13__ESDHC1_DAT5 0x090 0x288 0x4d0 0x06 0x000
#define MX25_PAD_D12__D12 0x094 0x28c 0x000 0x00 0x000
#define MX25_PAD_D12__GPIO_4_8 0x094 0x28c 0x000 0x05 0x000
#define MX25_PAD_D12__SDHC1_DAT4 0x094 0x28c 0x4cc 0x06 0x000
#define MX25_PAD_D12__ESDHC1_DAT4 0x094 0x28c 0x4cc 0x06 0x000
#define MX25_PAD_D11__D11 0x098 0x290 0x000 0x00 0x000
#define MX25_PAD_D11__GPIO_4_9 0x098 0x290 0x000 0x05 0x000
@ -236,12 +236,13 @@
#define MX25_PAD_LD8__LD8 0x0e8 0x2e0 0x000 0x00 0x000
#define MX25_PAD_LD8__UART4_RXD 0x0e8 0x2e0 0x570 0x02 0x000
#define MX25_PAD_LD8__FEC_TX_ERR 0x0e8 0x2e0 0x000 0x05 0x000
#define MX25_PAD_LD8__SDHC2_CMD 0x0e8 0x2e0 0x4e0 0x06 0x000
/* SION must be set; see the comment for MX25_PAD_SD1_CMD__ESDHC1_CMD. */
#define MX25_PAD_LD8__ESDHC2_CMD 0x0e8 0x2e0 0x4e0 0x16 0x000
#define MX25_PAD_LD9__LD9 0x0ec 0x2e4 0x000 0x00 0x000
#define MX25_PAD_LD9__UART4_TXD 0x0ec 0x2e4 0x000 0x02 0x000
#define MX25_PAD_LD9__FEC_COL 0x0ec 0x2e4 0x504 0x05 0x001
#define MX25_PAD_LD9__SDHC2_CLK 0x0ec 0x2e4 0x4dc 0x06 0x000
#define MX25_PAD_LD9__ESDHC2_CLK 0x0ec 0x2e4 0x4dc 0x06 0x000
#define MX25_PAD_LD10__LD10 0x0f0 0x2e8 0x000 0x00 0x000
#define MX25_PAD_LD10__UART4_RTS 0x0f0 0x2e8 0x56c 0x02 0x000
@ -250,7 +251,7 @@
#define MX25_PAD_LD11__LD11 0x0f4 0x2ec 0x000 0x00 0x000
#define MX25_PAD_LD11__UART4_CTS 0x0f4 0x2ec 0x000 0x02 0x000
#define MX25_PAD_LD11__FEC_RDATA2 0x0f4 0x2ec 0x50c 0x05 0x001
#define MX25_PAD_LD11__SDHC2_DAT1 0x0f4 0x2ec 0x4e8 0x06 0x000
#define MX25_PAD_LD11__ESDHC2_DAT1 0x0f4 0x2ec 0x4e8 0x06 0x000
#define MX25_PAD_LD12__LD12 0x0f8 0x2f0 0x000 0x00 0x000
#define MX25_PAD_LD12__CSPI2_MOSI 0x0f8 0x2f0 0x4a0 0x02 0x000
@ -316,12 +317,13 @@
#define MX25_PAD_CSI_D5__CSPI3_RDY 0x12c 0x324 0x000 0x07 0x000
#define MX25_PAD_CSI_D6__CSI_D6 0x130 0x328 0x000 0x00 0x000
#define MX25_PAD_CSI_D6__SDHC2_CMD 0x130 0x328 0x4e0 0x02 0x001
/* SION must be set; see the comment for MX25_PAD_SD1_CMD__ESDHC1_CMD. */
#define MX25_PAD_CSI_D6__ESDHC2_CMD 0x130 0x328 0x4e0 0x12 0x001
#define MX25_PAD_CSI_D6__SIM1_PD0 0x130 0x328 0x000 0x04 0x000
#define MX25_PAD_CSI_D6__GPIO_1_31 0x130 0x328 0x000 0x05 0x000
#define MX25_PAD_CSI_D7__CSI_D7 0x134 0x32c 0x000 0x00 0x000
#define MX25_PAD_CSI_D7__SDHC2_DAT_CLK 0x134 0x32C 0x4dc 0x02 0x001
#define MX25_PAD_CSI_D7__ESDHC2_CLK 0x134 0x32C 0x4dc 0x02 0x001
#define MX25_PAD_CSI_D7__GPIO_1_6 0x134 0x32c 0x000 0x05 0x000
#define MX25_PAD_CSI_D8__CSI_D8 0x138 0x330 0x000 0x00 0x000
@ -336,22 +338,22 @@
#define MX25_PAD_CSI_MCLK__CSI_MCLK 0x140 0x338 0x000 0x00 0x000
#define MX25_PAD_CSI_MCLK__AUD6_TXD 0x140 0x338 0x000 0x01 0x000
#define MX25_PAD_CSI_MCLK__SDHC2_DAT0 0x140 0x338 0x4e4 0x02 0x001
#define MX25_PAD_CSI_MCLK__ESDHC2_DAT0 0x140 0x338 0x4e4 0x02 0x001
#define MX25_PAD_CSI_MCLK__GPIO_1_8 0x140 0x338 0x000 0x05 0x000
#define MX25_PAD_CSI_VSYNC__CSI_VSYNC 0x144 0x33c 0x000 0x00 0x000
#define MX25_PAD_CSI_VSYNC__AUD6_RXD 0x144 0x33c 0x000 0x01 0x000
#define MX25_PAD_CSI_VSYNC__SDHC2_DAT1 0x144 0x33c 0x4e8 0x02 0x001
#define MX25_PAD_CSI_VSYNC__ESDHC2_DAT1 0x144 0x33c 0x4e8 0x02 0x001
#define MX25_PAD_CSI_VSYNC__GPIO_1_9 0x144 0x33c 0x000 0x05 0x000
#define MX25_PAD_CSI_HSYNC__CSI_HSYNC 0x148 0x340 0x000 0x00 0x000
#define MX25_PAD_CSI_HSYNC__AUD6_TXC 0x148 0x340 0x000 0x01 0x000
#define MX25_PAD_CSI_HSYNC__SDHC2_DAT2 0x148 0x340 0x4ec 0x02 0x001
#define MX25_PAD_CSI_HSYNC__ESDHC2_DAT2 0x148 0x340 0x4ec 0x02 0x001
#define MX25_PAD_CSI_HSYNC__GPIO_1_10 0x148 0x340 0x000 0x05 0x000
#define MX25_PAD_CSI_PIXCLK__CSI_PIXCLK 0x14c 0x344 0x000 0x00 0x000
#define MX25_PAD_CSI_PIXCLK__AUD6_TXFS 0x14c 0x344 0x000 0x01 0x000
#define MX25_PAD_CSI_PIXCLK__SDHC2_DAT3 0x14c 0x344 0x4f0 0x02 0x001
#define MX25_PAD_CSI_PIXCLK__ESDHC2_DAT3 0x14c 0x344 0x4f0 0x02 0x001
#define MX25_PAD_CSI_PIXCLK__GPIO_1_11 0x14c 0x344 0x000 0x05 0x000
#define MX25_PAD_I2C1_CLK__I2C1_CLK 0x150 0x348 0x000 0x00 0x000
@ -419,37 +421,37 @@
#define MX25_PAD_UART2_CTS__GPIO_4_29 0x18c 0x384 0x000 0x05 0x000
/*
* Removing the SION bit from MX25_PAD_SD1_CMD__SD1_CMD breaks detecting an SD
* Removing the SION bit from MX25_PAD_*__ESDHCn_CMD breaks detecting an SD
* card. According to the i.MX25 reference manual (e.g. Figure 23-2 in IMX25RM
* Rev. 2 from 01/2011) this pin is bidirectional. So it seems to be a silicon
* bug that configuring the SD1_CMD function doesn't enable the input path for
* this pin.
* bug that configuring the ESDHCn_CMD function doesn't enable the input path
* for this pin.
* This might have side effects for other hardware units that are connected to
* that pin and use the respective function as input.
*/
#define MX25_PAD_SD1_CMD__SD1_CMD 0x190 0x388 0x000 0x10 0x000
#define MX25_PAD_SD1_CMD__ESDHC1_CMD 0x190 0x388 0x000 0x10 0x000
#define MX25_PAD_SD1_CMD__CSPI2_MOSI 0x190 0x388 0x4a0 0x01 0x001
#define MX25_PAD_SD1_CMD__FEC_RDATA2 0x190 0x388 0x50c 0x02 0x002
#define MX25_PAD_SD1_CMD__GPIO_2_23 0x190 0x388 0x000 0x05 0x000
#define MX25_PAD_SD1_CLK__SD1_CLK 0x194 0x38c 0x000 0x00 0x000
#define MX25_PAD_SD1_CLK__ESDHC1_CLK 0x194 0x38c 0x000 0x00 0x000
#define MX25_PAD_SD1_CLK__CSPI2_MISO 0x194 0x38c 0x49c 0x01 0x001
#define MX25_PAD_SD1_CLK__FEC_RDATA3 0x194 0x38c 0x510 0x02 0x002
#define MX25_PAD_SD1_CLK__GPIO_2_24 0x194 0x38c 0x000 0x05 0x000
#define MX25_PAD_SD1_DATA0__SD1_DATA0 0x198 0x390 0x000 0x00 0x000
#define MX25_PAD_SD1_DATA0__ESDHC1_DAT0 0x198 0x390 0x000 0x00 0x000
#define MX25_PAD_SD1_DATA0__CSPI2_SCLK 0x198 0x390 0x494 0x01 0x001
#define MX25_PAD_SD1_DATA0__GPIO_2_25 0x198 0x390 0x000 0x05 0x000
#define MX25_PAD_SD1_DATA1__SD1_DATA1 0x19c 0x394 0x000 0x00 0x000
#define MX25_PAD_SD1_DATA1__ESDHC1_DAT1 0x19c 0x394 0x000 0x00 0x000
#define MX25_PAD_SD1_DATA1__AUD7_RXD 0x19c 0x394 0x478 0x03 0x000
#define MX25_PAD_SD1_DATA1__GPIO_2_26 0x19c 0x394 0x000 0x05 0x000
#define MX25_PAD_SD1_DATA2__SD1_DATA2 0x1a0 0x398 0x000 0x00 0x000
#define MX25_PAD_SD1_DATA2__ESDHC1_DAT2 0x1a0 0x398 0x000 0x00 0x000
#define MX25_PAD_SD1_DATA2__FEC_RX_CLK 0x1a0 0x398 0x514 0x02 0x002
#define MX25_PAD_SD1_DATA2__GPIO_2_27 0x1a0 0x398 0x000 0x05 0x000
#define MX25_PAD_SD1_DATA3__SD1_DATA3 0x1a4 0x39c 0x000 0x00 0x000
#define MX25_PAD_SD1_DATA3__ESDHC1_DAT3 0x1a4 0x39c 0x000 0x00 0x000
#define MX25_PAD_SD1_DATA3__FEC_CRS 0x1a4 0x39c 0x508 0x02 0x002
#define MX25_PAD_SD1_DATA3__GPIO_2_28 0x1a4 0x39c 0x000 0x05 0x000
@ -496,6 +498,8 @@
#define MX25_PAD_KPP_COL3__GPIO_3_4 0x1c4 0x3bc 0x000 0x05 0x000
#define MX25_PAD_FEC_MDC__FEC_MDC 0x1c8 0x3c0 0x000 0x00 0x000
/* SION must be set; see the comment for MX25_PAD_SD1_CMD__ESDHC1_CMD. */
#define MX25_PAD_FEC_MDC__ESDHC2_CMD 0x1c8 0x3c0 0x4e0 0x11 0x002
#define MX25_PAD_FEC_MDC__AUD4_TXD 0x1c8 0x3c0 0x464 0x02 0x001
#define MX25_PAD_FEC_MDC__GPIO_3_5 0x1c8 0x3c0 0x000 0x05 0x000
@ -601,4 +605,28 @@
#define MX25_PAD_BOOT_MODE1__BOOT_MODE1 0x228 0x000 0x000 0x00 0x000
#define MX25_PAD_BOOT_MODE1__GPIO_4_31 0x228 0x000 0x000 0x05 0x000
/*
* Compatibility defines for out-of-tree users. You should update if you make
* use of one of them.
*/
#define MX25_PAD_D15__SDHC1_DAT7 MX25_PAD_D15__ESDHC1_DAT7
#define MX25_PAD_D14__SDHC1_DAT6 MX25_PAD_D14__ESDHC1_DAT6
#define MX25_PAD_D13__SDHC1_DAT5 MX25_PAD_D13__ESDHC1_DAT5
#define MX25_PAD_D12__SDHC1_DAT4 MX25_PAD_D12__ESDHC1_DAT4
#define MX25_PAD_LD8__SDHC2_CMD MX25_PAD_LD8__ESDHC2_CMD
#define MX25_PAD_LD9__SDHC2_CLK MX25_PAD_LD9__ESDHC2_CLK
#define MX25_PAD_LD11__SDHC2_DAT1 MX25_PAD_LD11__ESDHC2_DAT1
#define MX25_PAD_CSI_D6__SDHC2_CMD MX25_PAD_CSI_D6__ESDHC2_CMD
#define MX25_PAD_CSI_D7__SDHC2_DAT_CLK MX25_PAD_CSI_D7__ESDHC2_CLK
#define MX25_PAD_CSI_MCLK__SDHC2_DAT0 MX25_PAD_CSI_MCLK__ESDHC2_DAT0
#define MX25_PAD_CSI_VSYNC__SDHC2_DAT1 MX25_PAD_CSI_VSYNC__ESDHC2_DAT1
#define MX25_PAD_CSI_HSYNC__SDHC2_DAT2 MX25_PAD_CSI_HSYNC__ESDHC2_DAT2
#define MX25_PAD_CSI_PIXCLK__SDHC2_DAT3 MX25_PAD_CSI_PIXCLK__ESDHC2_DAT3
#define MX25_PAD_SD1_CMD__SD1_CMD MX25_PAD_SD1_CMD__ESDHC1_CMD
#define MX25_PAD_SD1_CLK__SD1_CLK MX25_PAD_SD1_CLK__ESDHC1_CLK
#define MX25_PAD_SD1_DATA0__SD1_DATA0 MX25_PAD_SD1_DATA0__ESDHC1_DAT0
#define MX25_PAD_SD1_DATA1__SD1_DATA1 MX25_PAD_SD1_DATA1__ESDHC1_DAT1
#define MX25_PAD_SD1_DATA2__SD1_DATA2 MX25_PAD_SD1_DATA2__ESDHC1_DAT2
#define MX25_PAD_SD1_DATA3__SD1_DATA3 MX25_PAD_SD1_DATA3__ESDHC1_DAT3
#endif /* __DTS_IMX25_PINFUNC_H */

4
arch/arm/boot/dts/imx25.dtsi
View file

@ -22,7 +22,7 @@ / {
* Also for U-Boot there must be a pre-existing /memory node.
*/
chosen {};
memory { device_type = "memory"; reg = <0 0>; };
memory { device_type = "memory"; };
aliases {
ethernet0 = &fec;
@ -269,6 +269,7 @@ ssi2: ssi@50014000 {
dmas = <&sdma 24 1 0>,
<&sdma 25 1 0>;
dma-names = "rx", "tx";
fsl,fifo-depth = <15>;
status = "disabled";
};
@ -329,6 +330,7 @@ ssi1: ssi@50034000 {
dmas = <&sdma 28 1 0>,
<&sdma 29 1 0>;
dma-names = "rx", "tx";
fsl,fifo-depth = <15>;
status = "disabled";
};

2
arch/arm/boot/dts/imx27-apf27.dts
View file

@ -19,7 +19,7 @@ / {
model = "Armadeus Systems APF27 module";
compatible = "armadeus,imx27-apf27", "fsl,imx27";
memory {
memory@a0000000 {
reg = <0xa0000000 0x04000000>;
};

17
arch/arm/boot/dts/imx27-eukrea-cpuimx27.dtsi
View file

@ -16,21 +16,14 @@ / {
model = "Eukrea CPUIMX27";
compatible = "eukrea,cpuimx27", "fsl,imx27";
memory {
memory@a0000000 {
reg = <0xa0000000 0x04000000>;
};
clocks {
#address-cells = <1>;
#size-cells = <0>;
compatible = "simple-bus";
clk14745600: clock@0 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <14745600>;
reg = <0>;
};
clk14745600: clk-uart {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <14745600>;
};
};

2
arch/arm/boot/dts/imx27-eukrea-mbimxsd27-baseboard.dts
View file

@ -84,7 +84,7 @@ &cspi1 {
cs-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>;
status = "okay";
ads7846 {
ads7846@0 {
compatible = "ti,ads7846";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_touch>;

2
arch/arm/boot/dts/imx27-pdk.dts
View file

@ -16,7 +16,7 @@ / {
model = "Freescale i.MX27 Product Development Kit";
compatible = "fsl,imx27-pdk", "fsl,imx27";
memory {
memory@a0000000 {
reg = <0xa0000000 0x08000000>;
};

2
arch/arm/boot/dts/imx27-phytec-phycard-s-som.dtsi
View file

@ -17,7 +17,7 @@ / {
model = "Phytec pca100";
compatible = "phytec,imx27-pca100", "fsl,imx27";
memory {
memory@a0000000 {
reg = <0xa0000000 0x08000000>; /* 128MB */
};
};

2
arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi
View file

@ -16,7 +16,7 @@ / {
model = "Phytec pcm038";
compatible = "phytec,imx27-pcm038", "fsl,imx27";
memory {
memory@a0000000 {
reg = <0xa0000000 0x08000000>;
};

2
arch/arm/boot/dts/imx27.dtsi
View file

@ -26,7 +26,7 @@ / {
* Also for U-Boot there must be a pre-existing /memory node.
*/
chosen {};
memory { device_type = "memory"; reg = <0 0>; };
memory { device_type = "memory"; };
aliases {
ethernet0 = &fec;

2
arch/arm/boot/dts/imx28-apf28.dts
View file

@ -16,7 +16,7 @@ / {
model = "Armadeus Systems APF28 module";
compatible = "armadeus,imx28-apf28", "fsl,imx28";
memory {
memory@40000000 {
reg = <0x40000000 0x08000000>;
};

6
arch/arm/boot/dts/imx28-apx4devkit.dts
View file

@ -6,7 +6,7 @@ / {
model = "Bluegiga APX4 Development Kit";
compatible = "bluegiga,apx4devkit", "fsl,imx28";
memory {
memory@40000000 {
reg = <0x40000000 0x04000000>;
};
@ -82,7 +82,8 @@ MX28_PAD_SSP2_SS2__SSP2_D2
fsl,pull-up = <MXS_PULL_ENABLE>;
};
mmc2_sck_cfg_apx4: mmc2-sck-cfg-apx4 {
mmc2_sck_cfg_apx4: mmc2-sck-cfg-apx4@0 {
reg = <0>;
fsl,pinmux-ids = <
MX28_PAD_SSP0_DATA7__SSP2_SCK
>;
@ -146,6 +147,7 @@ i2c0: i2c@80058000 {
sgtl5000: codec@a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
#sound-dai-cells = <0>;
VDDA-supply = <&reg_3p3v>;
VDDIO-supply = <&reg_3p3v>;
clocks = <&saif0>;

2
arch/arm/boot/dts/imx28-cfa10036.dts
View file

@ -16,7 +16,7 @@ / {
model = "Crystalfontz CFA-10036 Board";
compatible = "crystalfontz,cfa10036", "fsl,imx28";
memory {
memory@40000000 {
reg = <0x40000000 0x08000000>;
};

130
arch/arm/boot/dts/imx28-cfa10049.dts
View file

@ -19,6 +19,71 @@ / {
model = "Crystalfontz CFA-10049 Board";
compatible = "crystalfontz,cfa10049", "crystalfontz,cfa10036", "fsl,imx28";
i2cmux {
compatible = "i2c-mux-gpio";
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&i2cmux_pins_cfa10049>;
mux-gpios = <&gpio1 22 0 &gpio1 23 0>;
i2c-parent = <&i2c1>;
i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
adc0: nau7802@2a {
compatible = "nuvoton,nau7802";
reg = <0x2a>;
nuvoton,vldo = <3000>;
};
};
i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
adc1: nau7802@2a {
compatible = "nuvoton,nau7802";
reg = <0x2a>;
nuvoton,vldo = <3000>;
};
};
i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
adc2: nau7802@2a {
compatible = "nuvoton,nau7802";
reg = <0x2a>;
nuvoton,vldo = <3000>;
};
};
i2c@3 {
reg = <3>;
#address-cells = <1>;
#size-cells = <0>;
pca9555: pca9555@20 {
compatible = "nxp,pca9555";
pinctrl-names = "default";
pinctrl-0 = <&pca_pins_cfa10049>;
interrupt-parent = <&gpio2>;
interrupts = <19 0x2>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x20>;
};
};
};
apb@80000000 {
apbh@80000000 {
pinctrl@80018000 {
@ -219,71 +284,6 @@ i2c1: i2c@8005a000 {
status = "okay";
};
i2cmux {
compatible = "i2c-mux-gpio";
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&i2cmux_pins_cfa10049>;
mux-gpios = <&gpio1 22 0 &gpio1 23 0>;
i2c-parent = <&i2c1>;
i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
adc0: nau7802@2a {
compatible = "nuvoton,nau7802";
reg = <0x2a>;
nuvoton,vldo = <3000>;
};
};
i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
adc1: nau7802@2a {
compatible = "nuvoton,nau7802";
reg = <0x2a>;
nuvoton,vldo = <3000>;
};
};
i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
adc2: nau7802@2a {
compatible = "nuvoton,nau7802";
reg = <0x2a>;
nuvoton,vldo = <3000>;
};
};
i2c@3 {
reg = <3>;
#address-cells = <1>;
#size-cells = <0>;
pca9555: pca9555@20 {
compatible = "nxp,pca9555";
pinctrl-names = "default";
pinctrl-0 = <&pca_pins_cfa10049>;
interrupt-parent = <&gpio2>;
interrupts = <19 0x2>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x20>;
};
};
};
usbphy1: usbphy@8007e000 {
status = "okay";
};

2
arch/arm/boot/dts/imx28-duckbill-2-485.dts
View file

@ -19,7 +19,7 @@ / {
model = "I2SE Duckbill 2 485";
compatible = "i2se,duckbill-2-485", "i2se,duckbill-2", "fsl,imx28";
memory {
memory@40000000 {
reg = <0x40000000 0x08000000>;
};

2
arch/arm/boot/dts/imx28-duckbill-2-enocean.dts
View file

@ -20,7 +20,7 @@ / {
model = "I2SE Duckbill 2 EnOcean";
compatible = "i2se,duckbill-2-enocean", "i2se,duckbill-2", "fsl,imx28";
memory {
memory@40000000 {
reg = <0x40000000 0x08000000>;
};

2
arch/arm/boot/dts/imx28-duckbill-2-spi.dts
View file

@ -23,7 +23,7 @@ aliases {
ethernet1 = &qca7000;
};
memory {
memory@40000000 {
reg = <0x40000000 0x08000000>;
};

2
arch/arm/boot/dts/imx28-duckbill-2.dts
View file

@ -19,7 +19,7 @@ / {
model = "I2SE Duckbill 2";
compatible = "i2se,duckbill-2", "fsl,imx28";
memory {
memory@40000000 {
reg = <0x40000000 0x08000000>;
};

2
arch/arm/boot/dts/imx28-duckbill.dts
View file

@ -18,7 +18,7 @@ / {
model = "I2SE Duckbill";
compatible = "i2se,duckbill", "fsl,imx28";
memory {
memory@40000000 {
reg = <0x40000000 0x08000000>;
};

2
arch/arm/boot/dts/imx28-eukrea-mbmx283lc.dts
View file

@ -23,7 +23,7 @@ / {
model = "Eukrea Electromatique MBMX283LC";
compatible = "eukrea,mbmx283lc", "eukrea,mbmx28lc", "fsl,imx28";
memory {
memory@40000000 {
reg = <0x40000000 0x04000000>;
};
};

2
arch/arm/boot/dts/imx28-eukrea-mbmx287lc.dts
View file

@ -22,7 +22,7 @@ / {
model = "Eukrea Electromatique MBMX287LC";
compatible = "eukrea,mbmx287lc", "eukrea,mbmx283lc", "eukrea,mbmx28lc", "fsl,imx28";
memory {
memory@40000000 {
reg = <0x40000000 0x08000000>;
};
};

1
arch/arm/boot/dts/imx28-eukrea-mbmx28lc.dtsi
View file

@ -151,6 +151,7 @@ &i2c0 {
sgtl5000: codec@a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
#sound-dai-cells = <0>;
VDDA-supply = <&reg_3p3v>;
VDDIO-supply = <&reg_3p3v>;
clocks = <&saif0>;

3
arch/arm/boot/dts/imx28-evk.dts
View file

@ -16,7 +16,7 @@ / {
model = "Freescale i.MX28 Evaluation Kit";
compatible = "fsl,imx28-evk", "fsl,imx28";
memory {
memory@40000000 {
reg = <0x40000000 0x08000000>;
};
@ -197,6 +197,7 @@ i2c0: i2c@80058000 {
sgtl5000: codec@a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
#sound-dai-cells = <0>;
VDDA-supply = <&reg_3p3v>;
VDDIO-supply = <&reg_3p3v>;
clocks = <&saif0>;

2
arch/arm/boot/dts/imx28-m28.dtsi
View file

@ -15,7 +15,7 @@ / {
model = "Aries/DENX M28";
compatible = "aries,m28", "denx,m28", "fsl,imx28";
memory {
memory@40000000 {
reg = <0x40000000 0x08000000>;
};

2
arch/arm/boot/dts/imx28-m28cu3.dts
View file

@ -16,7 +16,7 @@ / {
model = "MSR M28CU3";
compatible = "msr,m28cu3", "fsl,imx28";
memory {
memory@40000000 {
reg = <0x40000000 0x08000000>;
};

1
arch/arm/boot/dts/imx28-m28evk.dts
View file

@ -140,6 +140,7 @@ i2c0: i2c@80058000 {
sgtl5000: codec@a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
#sound-dai-cells = <0>;
VDDA-supply = <&reg_3p3v>;
VDDIO-supply = <&reg_3p3v>;
clocks = <&saif0>;

2
arch/arm/boot/dts/imx28-sps1.dts
View file

@ -16,7 +16,7 @@ / {
model = "SchulerControl GmbH, SC SPS 1";
compatible = "schulercontrol,imx28-sps1", "fsl,imx28";
memory {
memory@40000000 {
reg = <0x40000000 0x08000000>;
};

2
arch/arm/boot/dts/imx28-ts4600.dts
View file

@ -19,7 +19,7 @@ / {
model = "Technologic Systems i.MX28 TS-4600";
compatible = "technologic,imx28-ts4600", "fsl,imx28";
memory {
memory@40000000 {
reg = <0x40000000 0x10000000>; /* 256MB */
};

34
arch/arm/boot/dts/imx28-tx28.dts
View file

@ -65,8 +65,8 @@ aliases {
usbotg = &usb0;
};
memory {
reg = <0 0>; /* will be filled in by U-Boot */
memory@40000000 {
reg = <0x40000000 0>; /* will be filled in by U-Boot */
};
onewire {
@ -531,7 +531,8 @@ MX28_PAD_ENET0_RXD3__GPIO_4_10 /* module LED */
fsl,pull-up = <MXS_PULL_DISABLE>;
};
tx28_edt_ft5x06_pins: tx28-edt-ft5x06-pins {
tx28_edt_ft5x06_pins: tx28-edt-ft5x06-pins@0 {
reg = <0>;
fsl,pinmux-ids = <
MX28_PAD_SSP0_DATA6__GPIO_2_6 /* RESET */
MX28_PAD_SSP0_DATA5__GPIO_2_5 /* IRQ */
@ -542,7 +543,8 @@ MX28_PAD_ENET0_RXD2__GPIO_4_9 /* WAKE */
fsl,pull-up = <MXS_PULL_DISABLE>;
};
tx28_flexcan_xcvr_pins: tx28-flexcan-xcvr-pins {
tx28_flexcan_xcvr_pins: tx28-flexcan-xcvr-pins@0 {
reg = <0>;
fsl,pinmux-ids = <
MX28_PAD_LCD_D00__GPIO_1_0
>;
@ -551,7 +553,8 @@ MX28_PAD_LCD_D00__GPIO_1_0
fsl,pull-up = <MXS_PULL_DISABLE>;
};
tx28_lcdif_23bit_pins: tx28-lcdif-23bit {
tx28_lcdif_23bit_pins: tx28-lcdif-23bit@0 {
reg = <0>;
fsl,pinmux-ids = <
/* LCD_D00 may be used as Flexcan Transceiver Enable on STK5-V5 */
MX28_PAD_LCD_D01__LCD_D1
@ -583,7 +586,8 @@ MX28_PAD_LCD_D23__LCD_D23
fsl,pull-up = <MXS_PULL_DISABLE>;
};
tx28_lcdif_ctrl_pins: tx28-lcdif-ctrl {
tx28_lcdif_ctrl_pins: tx28-lcdif-ctrl@0 {
reg = <0>;
fsl,pinmux-ids = <
MX28_PAD_LCD_ENABLE__GPIO_1_31 /* Enable */
MX28_PAD_LCD_RESET__GPIO_3_30 /* Reset */
@ -593,7 +597,8 @@ MX28_PAD_LCD_RESET__GPIO_3_30 /* Reset */
fsl,pull-up = <MXS_PULL_DISABLE>;
};
tx28_mac0_pins_gpio: tx28-mac0-gpio-pins {
tx28_mac0_pins_gpio: tx28-mac0-gpio-pins@0 {
reg = <0>;
fsl,pinmux-ids = <
MX28_PAD_ENET0_MDC__GPIO_4_0
MX28_PAD_ENET0_MDIO__GPIO_4_1
@ -610,7 +615,8 @@ MX28_PAD_ENET_CLK__GPIO_4_16
fsl,pull-up = <MXS_PULL_DISABLE>;
};
tx28_pca9554_pins: tx28-pca9554-pins {
tx28_pca9554_pins: tx28-pca9554-pins@0 {
reg = <0>;
fsl,pinmux-ids = <
MX28_PAD_PWM3__GPIO_3_28
>;
@ -619,7 +625,8 @@ MX28_PAD_PWM3__GPIO_3_28
fsl,pull-up = <MXS_PULL_DISABLE>;
};
tx28_spi_gpio_pins: spi-gpiogrp {
tx28_spi_gpio_pins: spi-gpiogrp@0 {
reg = <0>;
fsl,pinmux-ids = <
MX28_PAD_AUART2_RX__GPIO_3_8
MX28_PAD_AUART2_TX__GPIO_3_9
@ -633,7 +640,8 @@ MX28_PAD_SSP3_SS0__GPIO_2_27
fsl,pull-up = <MXS_PULL_DISABLE>;
};
tx28_tsc2007_pins: tx28-tsc2007-pins {
tx28_tsc2007_pins: tx28-tsc2007-pins@0 {
reg = <0>;
fsl,pinmux-ids = <
MX28_PAD_SAIF0_MCLK__GPIO_3_20 /* TSC2007 IRQ */
>;
@ -643,7 +651,8 @@ MX28_PAD_SAIF0_MCLK__GPIO_3_20 /* TSC2007 IRQ */
};
tx28_usbphy0_pins: tx28-usbphy0-pins {
tx28_usbphy0_pins: tx28-usbphy0-pins@0 {
reg = <0>;
fsl,pinmux-ids = <
MX28_PAD_GPMI_CE2N__GPIO_0_18 /* USBOTG_VBUSEN */
MX28_PAD_GPMI_CE3N__GPIO_0_19 /* USBOTH_OC */
@ -653,7 +662,8 @@ MX28_PAD_GPMI_CE3N__GPIO_0_19 /* USBOTH_OC */
fsl,pull-up = <MXS_PULL_DISABLE>;
};
tx28_usbphy1_pins: tx28-usbphy1-pins {
tx28_usbphy1_pins: tx28-usbphy1-pins@0 {
reg = <0>;
fsl,pinmux-ids = <
MX28_PAD_SPDIF__GPIO_3_27 /* USBH_VBUSEN */
MX28_PAD_JTAG_RTCK__GPIO_4_20 /* USBH_OC */

20
arch/arm/boot/dts/imx28.dtsi
View file

@ -24,7 +24,7 @@ / {
* Also for U-Boot there must be a pre-existing /memory node.
*/
chosen {};
memory { device_type = "memory"; reg = <0 0>; };
memory { device_type = "memory"; };
aliases {
ethernet0 = &mac0;
@ -283,7 +283,8 @@ MX28_PAD_GPMI_RESETN__GPMI_RESETN
fsl,pull-up = <MXS_PULL_DISABLE>;
};
gpmi_status_cfg: gpmi-status-cfg {
gpmi_status_cfg: gpmi-status-cfg@0 {
reg = <0>;
fsl,pinmux-ids = <
MX28_PAD_GPMI_RDN__GPMI_RDN
MX28_PAD_GPMI_WRN__GPMI_WRN
@ -527,14 +528,16 @@ MX28_PAD_SSP0_SCK__SSP0_SCK
fsl,pull-up = <MXS_PULL_ENABLE>;
};
mmc0_cd_cfg: mmc0-cd-cfg {
mmc0_cd_cfg: mmc0-cd-cfg@0 {
reg = <0>;
fsl,pinmux-ids = <
MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT
>;
fsl,pull-up = <MXS_PULL_DISABLE>;
};
mmc0_sck_cfg: mmc0-sck-cfg {
mmc0_sck_cfg: mmc0-sck-cfg@0 {
reg = <0>;
fsl,pinmux-ids = <
MX28_PAD_SSP0_SCK__SSP0_SCK
>;
@ -558,14 +561,16 @@ MX28_PAD_GPMI_WRN__SSP1_SCK
fsl,pull-up = <MXS_PULL_ENABLE>;
};
mmc1_cd_cfg: mmc1-cd-cfg {
mmc1_cd_cfg: mmc1-cd-cfg@0 {
reg = <0>;
fsl,pinmux-ids = <
MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT
>;
fsl,pull-up = <MXS_PULL_DISABLE>;
};
mmc1_sck_cfg: mmc1-sck-cfg {
mmc1_sck_cfg: mmc1-sck-cfg@0 {
reg = <0>;
fsl,pinmux-ids = <
MX28_PAD_GPMI_WRN__SSP1_SCK
>;
@ -606,7 +611,8 @@ MX28_PAD_AUART1_RX__SSP2_CARD_DETECT
fsl,pull-up = <MXS_PULL_ENABLE>;
};
mmc2_cd_cfg: mmc2-cd-cfg {
mmc2_cd_cfg: mmc2-cd-cfg@0 {
reg = <0>;
fsl,pinmux-ids = <
MX28_PAD_AUART1_RX__SSP2_CARD_DETECT
>;

2
arch/arm/boot/dts/imx31-bug.dts
View file

@ -16,7 +16,7 @@ / {
model = "Buglabs i.MX31 Bug 1.x";
compatible = "buglabs,imx31-bug", "fsl,imx31";
memory {
memory@80000000 {
reg = <0x80000000 0x8000000>; /* 128M */
};
};

2
arch/arm/boot/dts/imx31.dtsi
View file

@ -19,7 +19,7 @@ / {
* Also for U-Boot there must be a pre-existing /memory node.
*/
chosen {};
memory { device_type = "memory"; reg = <0 0>; };
memory { device_type = "memory"; };
aliases {
serial0 = &uart1;

2
arch/arm/boot/dts/imx35-eukrea-cpuimx35.dtsi
View file

@ -17,7 +17,7 @@ / {
model = "Eukrea CPUIMX35";
compatible = "eukrea,cpuimx35", "fsl,imx35";
memory {
memory@80000000 {
reg = <0x80000000 0x8000000>; /* 128M */
};
};

2
arch/arm/boot/dts/imx35-pdk.dts
View file

@ -17,7 +17,7 @@ / {
model = "Freescale i.MX35 Product Development Kit";
compatible = "fsl,imx35-pdk", "fsl,imx35";
memory {
memory@80000000 {
reg = <0x80000000 0x8000000>,
<0x90000000 0x8000000>;
};

2
arch/arm/boot/dts/imx35.dtsi
View file

@ -20,7 +20,7 @@ / {
* Also for U-Boot there must be a pre-existing /memory node.
*/
chosen {};
memory { device_type = "memory"; reg = <0 0>; };
memory { device_type = "memory"; };
aliases {
ethernet0 = &fec;

2
arch/arm/boot/dts/imx50-evk.dts
View file

@ -18,7 +18,7 @@ / {
model = "Freescale i.MX50 Evaluation Kit";
compatible = "fsl,imx50-evk", "fsl,imx50";
memory {
memory@70000000 {
reg = <0x70000000 0x80000000>;
};
};

2
arch/arm/boot/dts/imx50.dtsi
View file

@ -25,7 +25,7 @@ / {
* Also for U-Boot there must be a pre-existing /memory node.
*/
chosen {};
memory { device_type = "memory"; reg = <0 0>; };
memory { device_type = "memory"; };
aliases {
ethernet0 = &fec;

2
arch/arm/boot/dts/imx51-apf51.dts
View file

@ -21,7 +21,7 @@ / {
model = "Armadeus Systems APF51 module";
compatible = "armadeus,imx51-apf51", "fsl,imx51";
memory {
memory@90000000 {
reg = <0x90000000 0x20000000>;
};

3
arch/arm/boot/dts/imx51-babbage.dts
View file

@ -21,7 +21,7 @@ chosen {
stdout-path = &uart1;
};
memory {
memory@90000000 {
reg = <0x90000000 0x20000000>;
};
@ -369,6 +369,7 @@ &i2c2 {
sgtl5000: codec@a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
#sound-dai-cells = <0>;
clocks = <&clk_audio>;
VDDA-supply = <&vdig_reg>;
VDDIO-supply = <&vvideo_reg>;

2
arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi
View file

@ -16,7 +16,7 @@ / {
model = "Digi ConnectCore CC(W)-MX51";
compatible = "digi,connectcore-ccxmx51-som", "fsl,imx51";
memory {
memory@90000000 {
reg = <0x90000000 0x08000000>;
};
};

2
arch/arm/boot/dts/imx51-eukrea-cpuimx51.dtsi
View file

@ -22,7 +22,7 @@ / {
model = "Eukrea CPUIMX51";
compatible = "eukrea,cpuimx51", "fsl,imx51";
memory {
memory@90000000 {
reg = <0x90000000 0x10000000>; /* 256M */
};
};

2
arch/arm/boot/dts/imx51-ts4800.dts
View file

@ -17,7 +17,7 @@ chosen {
stdout-path = &uart1;
};
memory {
memory@90000000 {
reg = <0x90000000 0x10000000>;
};

14
arch/arm/boot/dts/imx51-zii-rdu1.dts
View file

@ -51,6 +51,11 @@ chosen {
stdout-path = &uart1;
};
/* Will be filled by the bootloader */
memory@90000000 {
reg = <0x90000000 0>;
};
aliases {
mdio-gpio0 = &mdio_gpio;
rtc0 = &ds1341;
@ -568,6 +573,15 @@ &uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
status = "okay";
rave-sp {
compatible = "zii,rave-sp-rdu1";
current-speed = <38400>;
watchdog {
compatible = "zii,rave-sp-watchdog";
};
};
};
&usbh1 {

2
arch/arm/boot/dts/imx51.dtsi
View file

@ -26,7 +26,7 @@ / {
* Also for U-Boot there must be a pre-existing /memory node.
*/
chosen {};
memory { device_type = "memory"; reg = <0 0>; };
memory { device_type = "memory"; };
aliases {
ethernet0 = &fec;

2
arch/arm/boot/dts/imx53-ard.dts
View file

@ -17,7 +17,7 @@ / {
model = "Freescale i.MX53 Automotive Reference Design Board";
compatible = "fsl,imx53-ard", "fsl,imx53";
memory {
memory@70000000 {
reg = <0x70000000 0x40000000>;
};

2
arch/arm/boot/dts/imx53-cx9020.dts
View file

@ -21,7 +21,7 @@ chosen {
stdout-path = &uart2;
};
memory {
memory@70000000 {
reg = <0x70000000 0x20000000>,
<0xb0000000 0x20000000>;
};

2
arch/arm/boot/dts/imx53-m53.dtsi
View file

@ -15,7 +15,7 @@ / {
model = "Aries/DENX M53";
compatible = "aries,imx53-m53", "denx,imx53-m53", "fsl,imx53";
memory {
memory@70000000 {
reg = <0x70000000 0x20000000>,
<0xb0000000 0x20000000>;
};

1
arch/arm/boot/dts/imx53-m53evk.dts
View file

@ -153,6 +153,7 @@ &i2c1 {
sgtl5000: codec@a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
#sound-dai-cells = <0>;
VDDA-supply = <&reg_3p2v>;
VDDIO-supply = <&reg_3p2v>;
clocks = <&clks IMX5_CLK_SSI_EXT1_GATE>;

12
arch/arm/boot/dts/imx53-ppd.dts
View file

@ -132,6 +132,14 @@ reg_usbh3_vbus: regulator-usbh3-vbus {
enable-active-high;
};
reg_tsiref: regulator-tsiref {
compatible = "regulator-fixed";
regulator-name = "tsiref";
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
regulator-always-on;
};
pwm_bl: backlight {
compatible = "pwm-backlight";
pwms = <&pwm2 0 50000>;
@ -294,6 +302,8 @@ da9053@0 {
interrupt-parent = <&gpio3>;
interrupts = <12 0x8>;
spi-max-frequency = <1000000>;
dlg,tsi-as-adc;
tsiref-supply = <&reg_tsiref>;
regulators {
buck1_reg: buck1 {
@ -436,6 +446,7 @@ i2c4: i2c@0 {
sgtl5000: codec@a {
compatible = "fsl,sgtl5000";
reg = <0xa>;
#sound-dai-cells = <0>;
VDDA-supply = <&reg_sgtl5k>;
VDDIO-supply = <&reg_sgtl5k>;
clocks = <&cko2_11M>;
@ -525,6 +536,7 @@ &i2c2 {
touchscreen@4b {
compatible = "atmel,maxtouch";
reset-gpio = <&gpio5 19 GPIO_ACTIVE_HIGH>;
reg = <0x4b>;
interrupt-parent = <&gpio5>;
interrupts = <4 0x8>;

3
arch/arm/boot/dts/imx53-qsb-common.dtsi
View file

@ -17,7 +17,7 @@ chosen {
stdout-path = &uart1;
};
memory {
memory@70000000 {
reg = <0x70000000 0x20000000>,
<0xb0000000 0x20000000>;
};
@ -317,6 +317,7 @@ &i2c2 {
sgtl5000: codec@a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
#sound-dai-cells = <0>;
VDDA-supply = <&reg_3p2v>;
VDDIO-supply = <&reg_3p2v>;
clocks = <&clks IMX5_CLK_SSI_EXT1_GATE>;

2
arch/arm/boot/dts/imx53-smd.dts
View file

@ -17,7 +17,7 @@ / {
model = "Freescale i.MX53 Smart Mobile Reference Design Board";
compatible = "fsl,imx53-smd", "fsl,imx53";
memory {
memory@70000000 {
reg = <0x70000000 0x40000000>;
};

2
arch/arm/boot/dts/imx53-tqma53.dtsi
View file

@ -16,7 +16,7 @@ / {
model = "TQ TQMa53";
compatible = "tq,tqma53", "fsl,imx53";
memory {
memory@70000000 {
reg = <0x70000000 0x40000000>; /* Up to 1GiB */
};

1
arch/arm/boot/dts/imx53-tx53-x03x.dts
View file

@ -230,6 +230,7 @@ &i2c3 {
sgtl5000: codec@a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
#sound-dai-cells = <0>;
VDDA-supply = <&reg_2v5>;
VDDIO-supply = <&reg_3v3>;
clocks = <&mclk>;

1
arch/arm/boot/dts/imx53-tx53-x13x.dts
View file

@ -131,6 +131,7 @@ &i2c3 {
sgtl5000: codec@a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
#sound-dai-cells = <0>;
VDDA-supply = <&reg_2v5>;
VDDIO-supply = <&reg_3v3>;
clocks = <&mclk>;

5
arch/arm/boot/dts/imx53-tx53.dtsi
View file

@ -49,6 +49,11 @@ / {
model = "Ka-Ro electronics TX53 module";
compatible = "karo,tx53", "fsl,imx53";
/* Will be filled by the bootloader */
memory@70000000 {
reg = <0x70000000 0>;
};
aliases {
can0 = &can2; /* Make the can interface indices consistent with TX28/TX48 modules */
can1 = &can1;

2
arch/arm/boot/dts/imx53-usbarmory.dts
View file

@ -57,7 +57,7 @@ chosen {
stdout-path = &uart1;
};
memory {
memory@70000000 {
reg = <0x70000000 0x20000000>;
};

1
arch/arm/boot/dts/imx53-voipac-bsb.dts
View file

@ -133,6 +133,7 @@ &i2c3 {
sgtl5000: codec@a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
#sound-dai-cells = <0>;
VDDA-supply = <&reg_3p3v>;
VDDIO-supply = <&reg_3p3v>;
clocks = <&clks 150>;

2
arch/arm/boot/dts/imx53.dtsi
View file

@ -26,7 +26,7 @@ / {
* Also for U-Boot there must be a pre-existing /memory node.
*/
chosen {};
memory { device_type = "memory"; reg = <0 0>; };
memory { device_type = "memory"; };
aliases {
ethernet0 = &fec;

2
arch/arm/boot/dts/imx6dl-apf6dev.dts
View file

@ -54,7 +54,7 @@ / {
model = "Armadeus APF6 Solo Module on APF6Dev Board";
compatible = "armadeus,imx6dl-apf6dev", "armadeus,imx6dl-apf6", "fsl,imx6dl";
memory {
memory@10000000 {
reg = <0x10000000 0x20000000>;
};
};

2
arch/arm/boot/dts/imx6dl-aristainetos2_4.dts
View file

@ -48,7 +48,7 @@ / {
model = "aristainetos2 i.MX6 Dual Lite Board 4";
compatible = "fsl,imx6dl";
memory {
memory@10000000 {
reg = <0x10000000 0x40000000>;
};

2
arch/arm/boot/dts/imx6dl-aristainetos2_7.dts
View file

@ -48,7 +48,7 @@ / {
model = "aristainetos2 i.MX6 Dual Lite Board 7";
compatible = "fsl,imx6dl";
memory {
memory@10000000 {
reg = <0x10000000 0x40000000>;
};

2
arch/arm/boot/dts/imx6dl-aristainetos_4.dts
View file

@ -27,7 +27,7 @@ backlight {
status = "okay";
};
memory {
memory@10000000 {
reg = <0x10000000 0x40000000>;
};

2
arch/arm/boot/dts/imx6dl-aristainetos_7.dts
View file

@ -16,7 +16,7 @@ / {
model = "aristainetos i.MX6 Dual Lite Board 7";
compatible = "fsl,imx6dl";
memory {
memory@10000000 {
reg = <0x10000000 0x40000000>;
};

9
arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts
View file

@ -53,6 +53,11 @@ / {
compatible = "toradex,colibri_imx6dl-eval-v3", "toradex,colibri_imx6dl",
"fsl,imx6dl";
/* Will be filled by the bootloader */
memory@10000000 {
reg = <0x10000000 0>;
};
aliases {
i2c0 = &i2c2;
i2c1 = &i2c3;
@ -63,6 +68,10 @@ aliases {
rtc1 = &snvs_rtc;
};
chosen {
stdout-path = "serial0:115200n8";
};
clocks {
/* Fixed crystal dedicated to mcp251x */
clk16m: clk@1 {

5
arch/arm/boot/dts/imx6dl-dfi-fs700-m60.dts
View file

@ -20,4 +20,9 @@
/ {
model = "DFI FS700-M60-6DL i.MX6dl Q7 Board";
compatible = "dfi,fs700-m60-6dl", "dfi,fs700e-m60", "fsl,imx6dl";
/* Will be filled by the bootloader */
memory@10000000 {
reg = <0x10000000 0>;
};
};

64
arch/arm/boot/dts/imx6dl-phytec-mira-rdk-nand.dts Normal file
View file

@ -0,0 +1,64 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2018 PHYTEC Messtechnik GmbH
* Author: Christian Hemp <c.hemp@phytec.de>
*/
/dts-v1/;
#include "imx6dl.dtsi"
#include "imx6qdl-phytec-phycore-som.dtsi"
#include "imx6qdl-phytec-mira.dtsi"
/ {
model = "PHYTEC phyBOARD-Mira DualLite/Solo Carrier-Board with NAND";
compatible = "phytec,imx6dl-pbac06-nand", "phytec,imx6dl-pbac06",
"phytec,imx6qdl-pcm058", "fsl,imx6dl";
chosen {
linux,stdout-path = &uart2;
};
};
&ethphy {
max-speed = <100>;
};
&fec {
status = "okay";
};
&gpmi {
status = "okay";
};
&hdmi {
status = "okay";
};
&i2c1 {
status = "okay";
};
&i2c2 {
status = "okay";
};
&i2c_rtc {
status = "okay";
};
&uart3 {
status = "okay";
};
&usbh1 {
status = "okay";
};
&usbotg {
status = "okay";
};
&usdhc1 {
status = "okay";
};

2
arch/arm/boot/dts/imx6dl-phytec-pfla02.dtsi
View file

@ -16,7 +16,7 @@ / {
model = "Phytec phyFLEX-i.MX6 DualLite/Solo";
compatible = "phytec,imx6dl-pfla02", "fsl,imx6dl";
memory {
memory@10000000 {
reg = <0x10000000 0x20000000>;
};
};

2
arch/arm/boot/dts/imx6dl-rex-basic.dts
View file

@ -16,7 +16,7 @@ / {
model = "Rex Basic i.MX6 Dual Lite Board";
compatible = "rex,imx6dl-rex-basic", "fsl,imx6dl";
memory {
memory@10000000 {
reg = <0x10000000 0x20000000>;
};
};

2
arch/arm/boot/dts/imx6dl-riotboard.dts
View file

@ -15,7 +15,7 @@ / {
model = "RIoTboard i.MX6S";
compatible = "riot,imx6s-riotboard", "fsl,imx6dl";
memory {
memory@10000000 {
reg = <0x10000000 0x40000000>;
};

5
arch/arm/boot/dts/imx6dl-ts4900.dts
View file

@ -46,4 +46,9 @@
/ {
model = "Technologic Systems i.MX6 Solo/DualLite TS-4900 (Default Device Tree)";
compatible = "technologic,imx6dl-ts4900", "fsl,imx6dl";
/* Will be filled by the bootloader */
memory@10000000 {
reg = <0x10000000 0>;
};
};

5
arch/arm/boot/dts/imx6dl-ts7970.dts
View file

@ -47,4 +47,9 @@
/ {
model = "Technologic Systems i.MX6 Solo/DualLite TS-7970 (Default Device Tree)";
compatible = "technologic,imx6dl-ts7970", "fsl,imx6dl";
/* Will be filled by the bootloader */
memory@10000000 {
reg = <0x10000000 0>;
};
};

2
arch/arm/boot/dts/imx6dl-wandboard-revb1.dts
View file

@ -16,7 +16,7 @@ / {
model = "Wandboard i.MX6 Dual Lite Board rev B1";
compatible = "wand,imx6dl-wandboard", "fsl,imx6dl";
memory {
memory@10000000 {
reg = <0x10000000 0x40000000>;
};
};

2
arch/arm/boot/dts/imx6dl-wandboard-revd1.dts
View file

@ -16,7 +16,7 @@ / {
model = "Wandboard i.MX6 Dual Lite Board revD1";
compatible = "wand,imx6dl-wandboard", "fsl,imx6dl";
memory {
memory@10000000 {
reg = <0x10000000 0x40000000>;
};
};

2
arch/arm/boot/dts/imx6dl-wandboard.dts
View file

@ -16,7 +16,7 @@ / {
model = "Wandboard i.MX6 Dual Lite Board";
compatible = "wand,imx6dl-wandboard", "fsl,imx6dl";
memory {
memory@10000000 {
reg = <0x10000000 0x40000000>;
};
};

10
arch/arm/boot/dts/imx6dl.dtsi
View file

@ -80,11 +80,6 @@ epdc: epdc@20f4000 {
reg = <0x020f4000 0x4000>;
interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
};
lcdif: lcdif@20f8000 {
reg = <0x020f8000 0x4000>;
interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
};
};
aips2: aips-bus@2100000 {
@ -109,11 +104,6 @@ display-subsystem {
compatible = "fsl,imx-display-subsystem";
ports = <&ipu1_di0>, <&ipu1_di1>;
};
gpu-subsystem {
compatible = "fsl,imx-gpu-subsystem";
cores = <&gpu_2d>, <&gpu_3d>;
};
};
&gpio1 {

2
arch/arm/boot/dts/imx6q-apf6dev.dts
View file

@ -54,7 +54,7 @@ / {
model = "Armadeus APF6 Quad / Dual Module on APF6Dev Board";
compatible = "armadeus,imx6q-apf6dev", "armadeus,imx6q-apf6", "fsl,imx6q";
memory {
memory@10000000 {
reg = <0x10000000 0x40000000>;
};
};

2
arch/arm/boot/dts/imx6q-arm2.dts
View file

@ -18,7 +18,7 @@ / {
model = "Freescale i.MX6 Quad Armadillo2 Board";
compatible = "fsl,imx6q-arm2", "fsl,imx6q";
memory {
memory@10000000 {
reg = <0x10000000 0x80000000>;
};

2
arch/arm/boot/dts/imx6q-ba16.dtsi
View file

@ -46,7 +46,7 @@
#include <dt-bindings/gpio/gpio.h>
/ {
memory {
memory@10000000 {
reg = <0x10000000 0x40000000>;
};

8
arch/arm/boot/dts/imx6q-bx50v3.dtsi
View file

@ -353,6 +353,14 @@ MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b0
};
};
&pmu {
secure-reg-access;
};
&usdhc2 {
status = "disabled";
};
&usdhc4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc4>;

2
arch/arm/boot/dts/imx6q-cm-fx6.dts
View file

@ -50,7 +50,7 @@ / {
model = "CompuLab CM-FX6";
compatible = "compulab,cm-fx6", "fsl,imx6q";
memory {
memory@10000000 {
reg = <0x10000000 0x80000000>;
};

5
arch/arm/boot/dts/imx6q-dfi-fs700-m60.dts
View file

@ -20,4 +20,9 @@
/ {
model = "DFI FS700-M60-6QD i.MX6qd Q7 Board";
compatible = "dfi,fs700-m60-6qd", "dfi,fs700e-m60", "fsl,imx6q";
/* Will be filled by the bootloader */
memory@10000000 {
reg = <0x10000000 0>;
};
};

2
arch/arm/boot/dts/imx6q-display5.dtsi
View file

@ -47,7 +47,7 @@ / {
model = "Liebherr (LWN) display5 i.MX6 Quad Board";
compatible = "lwn,display5", "fsl,imx6q";
memory {
memory@10000000 {
reg = <0x10000000 0x40000000>;
};

2
arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts
View file

@ -29,7 +29,7 @@ aliases {
stmpe-i2c1 = &stmpe2;
};
memory {
memory@10000000 {
reg = <0x10000000 0x80000000>;
};

139
arch/arm/boot/dts/imx6q-dms-ba16.dts Normal file
View file

@ -0,0 +1,139 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include "imx6q-ba16.dtsi"
/ {
model = "Advantech DMS-BA16";
compatible = "advantech,imx6q-dms-ba16", "advantech,imx6q-ba16", "fsl,imx6q";
reg_usb_otg_vbus: regulator-usbotgvbus {
compatible = "regulator-fixed";
regulator-name = "usb_otg_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotgvbus>;
gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
sys_mclk: clock-sys-mclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <22000000>;
};
sound {
compatible = "fsl,imx6q-ba16-sgtl5000",
"fsl,imx-audio-sgtl5000";
model = "imx6q-ba16-sgtl5000";
ssi-controller = <&ssi1>;
audio-codec = <&sgtl5000>;
audio-routing =
"MIC_IN", "Mic Jack",
"Mic Jack", "Mic Bias",
"Headphone Jack", "HP_OUT";
mux-int-port = <1>;
mux-ext-port = <4>;
};
};
&ecspi5 {
cs-gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi5>;
status = "okay";
m25_eeprom: m25p80@0 {
compatible = "atmel,at25256B", "atmel,at25";
spi-max-frequency = <20000000>;
size = <0x8000>;
pagesize = <64>;
reg = <0>;
address-width = <16>;
};
};
&iomuxc {
pinctrl_i2c1_gpio: i2c1gpiogrp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x1b0b0
MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x1b0b0
>;
};
pinctrl_i2c2_gpio: i2c2gpiogrp {
fsl,pins = <
MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x1b0b0
MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x1b0b0
>;
};
pinctrl_i2c3_gpio: i2c3gpiogrp {
fsl,pins = <
MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x1b0b0
MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b0
>;
};
pinctrl_usbotgvbus: usbotgvbusgrp {
fsl,pins = <
MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x000b0
>;
};
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
sgtl5000: codec@a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
clocks = <&sys_mclk>;
lrclk-strength = <0x3>;
VDDA-supply = <&reg_1p8v>;
VDDIO-supply = <&reg_3p3v>;
};
};
&pwm2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm2>;
status = "okay";
};
&sata {
fsl,no-spread-spectrum;
fsl,transmit-atten-16ths = <12>;
fsl,transmit-boost-mdB = <3330>;
fsl,transmit-level-mV = <1133>;
fsl,receive-dpll-mode = <1>;
status = "okay";
};
&usbotg {
vbus-supply = <&reg_usb_otg_vbus>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg>;
dr_mode = "otg";
disable-over-current;
status = "okay";
};
&usdhc4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc4>;
bus-width = <8>;
cd-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
no-1-8-v;
keep-power-in-suspend;
wakeup-source;
status = "okay";
};

2
arch/arm/boot/dts/imx6q-evi.dts
View file

@ -50,7 +50,7 @@ / {
model = "Uniwest Evi";
compatible = "uniwest,imx6q-evi", "fsl,imx6q";
memory {
memory@10000000 {
reg = <0x10000000 0x40000000>;
};

2
arch/arm/boot/dts/imx6q-gk802.dts
View file

@ -18,7 +18,7 @@ chosen {
stdout-path = &uart4;
};
memory {
memory@10000000 {
reg = <0x10000000 0x40000000>;
};

2
arch/arm/boot/dts/imx6q-gw5400-a.dts
View file

@ -60,7 +60,7 @@ led2: user3 {
};
};
memory {
memory@10000000 {
reg = <0x10000000 0x40000000>;
};

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