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drm/amdgpu: Make UTCL2 snoop CPU caches 

On AMD APP APUs, to make UTCL2 snoop CPU caches, its not sufficient to
rely on xgmi connected flag so add the logic to use is_app_apu to
program the PDE_REQUEST_PHYSICAL bit correctly for gfxhub and mmhub
both.

Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Rajneesh Bhardwaj 2022-12-20 15:37:57 -05:00 committed by Alex Deucher
parent 85b45b6072
commit 7a7aaab021
2 changed files with 4 additions and 2 deletions
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3
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c
View File

@ -252,7 +252,8 @@ static void gfxhub_v1_2_xcc_init_cache_regs(struct amdgpu_device *adev,
WREG32_SOC15_RLC(GC, GET_INST(GC, i), regVM_L2_CNTL3, tmp);
tmp = regVM_L2_CNTL4_DEFAULT;
if (adev->gmc.xgmi.connected_to_cpu) {
/* For AMD APP APUs setup WC memory */
if (adev->gmc.xgmi.connected_to_cpu || adev->gmc.is_app_apu) {
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 1);
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 1);
} else {

3
drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c
View File

@ -257,7 +257,8 @@ static void mmhub_v1_8_init_cache_regs(struct amdgpu_device *adev)
WREG32_SOC15(MMHUB, i, regVM_L2_CNTL3, tmp);
tmp = regVM_L2_CNTL4_DEFAULT;
if (adev->gmc.xgmi.connected_to_cpu) {
/* For AMD APP APUs setup WC memory */
if (adev->gmc.xgmi.connected_to_cpu || adev->gmc.is_app_apu) {
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4,
VMC_TAP_PDE_REQUEST_PHYSICAL, 1);
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4,