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drm/amdgpu: save list length when fence is signaled
update the list first to avoid redundant checks. Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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1 changed files with 6 additions and 7 deletions
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@ -244,6 +244,12 @@ struct dma_fence *amdgpu_sync_peek_fence(struct amdgpu_sync *sync,
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struct dma_fence *f = e->fence;
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struct amd_sched_fence *s_fence = to_amd_sched_fence(f);
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if (dma_fence_is_signaled(f)) {
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hash_del(&e->node);
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dma_fence_put(f);
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kmem_cache_free(amdgpu_sync_slab, e);
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continue;
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}
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if (ring && s_fence) {
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/* For fences from the same ring it is sufficient
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* when they are scheduled.
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@ -256,13 +262,6 @@ struct dma_fence *amdgpu_sync_peek_fence(struct amdgpu_sync *sync,
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}
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}
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if (dma_fence_is_signaled(f)) {
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hash_del(&e->node);
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dma_fence_put(f);
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kmem_cache_free(amdgpu_sync_slab, e);
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continue;
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}
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return f;
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}
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