mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-24 01:41:39 +00:00
Staging: rtl8187se: remove unused definitions from r8180_hw.h
Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit is contained in:
Bartlomiej Zolnierkiewicz
Greg Kroah-Hartman
parent
b6d11c07e5
commit
7abb66eba4
1 changed files with 5 additions and 309 deletions
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@ -29,18 +29,10 @@
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#define BIT5 0x00000020
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#define BIT6 0x00000040
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#define BIT7 0x00000080
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#define BIT8 0x00000100
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#define BIT9 0x00000200
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#define BIT10 0x00000400
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#define BIT11 0x00000800
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#define BIT12 0x00001000
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#define BIT13 0x00002000
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#define BIT14 0x00004000
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#define BIT15 0x00008000
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#define BIT16 0x00010000
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#define BIT17 0x00020000
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#define BIT18 0x00040000
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#define BIT19 0x00080000
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#define BIT20 0x00100000
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#define BIT21 0x00200000
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#define BIT22 0x00400000
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@ -57,29 +49,14 @@
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#define MAX_SLEEP_TIME (10000)
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#define MIN_SLEEP_TIME (50)
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#define BB_ANTATTEN_CHAN14 0x0c
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#define BB_ANTENNA_B 0x40
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#define BB_HOST_BANG (1<<30)
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#define BB_HOST_BANG_EN (1<<2)
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#define BB_HOST_BANG_CLK (1<<1)
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#define BB_HOST_BANG_DATA 1
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#define ANAPARAM_TXDACOFF_SHIFT 27
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#define ANAPARAM_PWR0_MASK ((1<<30)|(1<<29)|(1<<28))
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#define ANAPARAM_PWR0_SHIFT 28
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#define ANAPARAM_PWR1_MASK ((1<<26)|(1<<25)|(1<<24)|(1<<23)|(1<<22)|(1<<21)|(1<<20))
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#define ANAPARAM_PWR1_SHIFT 20
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#define MAC0 0
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#define MAC1 1
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#define MAC2 2
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#define MAC3 3
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#define MAC4 4
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#define MAC5 5
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#define CMD 0x37
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#define CMD_RST_SHIFT 4
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#define CMD_RESERVED_MASK ((1<<1) | (1<<5) | (1<<6) | (1<<7))
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#define CMD_RX_ENABLE_SHIFT 3
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#define CMD_TX_ENABLE_SHIFT 2
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@ -96,13 +73,9 @@
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#define EPROM_W_SHIFT 1
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#define EPROM_R_SHIFT 0
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#define CONFIG2_DMA_POLLING_MODE_SHIFT 3
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#define INTA 0x3e
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#define INTA_TXOVERFLOW (1<<15)
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#define INTA_TIMEOUT (1<<14)
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#define INTA_BEACONTIMEOUT (1<<13)
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#define INTA_ATIM (1<<12)
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#define INTA_BEACONDESCERR (1<<11)
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#define INTA_BEACONDESCOK (1<<10)
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#define INTA_HIPRIORITYDESCERR (1<<9)
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#define INTA_HIPRIORITYDESCOK (1<<8)
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#define INTA_NORMPRIORITYDESCERR (1<<7)
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@ -111,9 +84,9 @@
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#define INTA_RXDESCERR (1<<4)
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#define INTA_LOWPRIORITYDESCERR (1<<3)
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#define INTA_LOWPRIORITYDESCOK (1<<2)
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#define INTA_RXCRCERR (1<<1)
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#define INTA_RXOK (1)
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#define INTA_MASK 0x3c
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#define RXRING_ADDR 0xe4 // page 0
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#define PGSELECT 0x5e
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#define PGSELECT_PG_SHIFT 0
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@ -131,20 +104,15 @@
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#define ACCEPT_MCAST_FRAME_SHIFT 2
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#define ACCEPT_ALLMAC_FRAME_SHIFT 0
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#define ACCEPT_NICMAC_FRAME_SHIFT 1
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#define RX_FIFO_THRESHOLD_MASK ((1<<13) | (1<<14) | (1<<15))
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#define RX_FIFO_THRESHOLD_SHIFT 13
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#define RX_FIFO_THRESHOLD_128 3
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#define RX_FIFO_THRESHOLD_256 4
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#define RX_FIFO_THRESHOLD_512 5
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#define RX_FIFO_THRESHOLD_1024 6
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#define RX_FIFO_THRESHOLD_NONE 7
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#define RX_AUTORESETPHY_SHIFT 28
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#define EPROM_TYPE_SHIFT 6
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#define TX_CONF 0x40
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#define TX_CONF_HEADER_AUTOICREMENT_SHIFT 30
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#define TX_LOOPBACK_SHIFT 17
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#define TX_LOOPBACK_MAC 1
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#define TX_LOOPBACK_BASEBAND 2
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#define TX_LOOPBACK_NONE 0
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#define TX_LOOPBACK_CONTINUE 3
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#define TX_LOOPBACK_MASK ((1<<17)|(1<<18))
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@ -158,21 +126,12 @@
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#define TX_DMA_POLLING_HIPRIORITY_SHIFT 6
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#define TX_DMA_POLLING_NORMPRIORITY_SHIFT 5
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#define TX_DMA_POLLING_LOWPRIORITY_SHIFT 4
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#define TX_DMA_STOP_BEACON_SHIFT 3
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#define TX_DMA_STOP_HIPRIORITY_SHIFT 2
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#define TX_DMA_STOP_NORMPRIORITY_SHIFT 1
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#define TX_DMA_STOP_LOWPRIORITY_SHIFT 0
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#define TX_MANAGEPRIORITY_RING_ADDR 0x0C
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#define TX_BKPRIORITY_RING_ADDR 0x10
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#define TX_BEPRIORITY_RING_ADDR 0x14
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#define TX_VIPRIORITY_RING_ADDR 0x20
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#define TX_VOPRIORITY_RING_ADDR 0x24
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#define TX_HIGHPRIORITY_RING_ADDR 0x28
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//AC_VI and Low priority share the sane queue
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#define TX_LOWPRIORITY_RING_ADDR TX_VIPRIORITY_RING_ADDR
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//AC_VO and Norm priority share the same queue
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#define TX_NORMPRIORITY_RING_ADDR TX_VOPRIORITY_RING_ADDR
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#define MAX_RX_DMA_MASK ((1<<8) | (1<<9) | (1<<10))
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#define MAX_RX_DMA_2048 7
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#define MAX_RX_DMA_1024 6
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@ -189,11 +148,7 @@
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#define ATIM 0x72
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#define EPROM_CS_SHIFT 3
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#define EPROM_CK_SHIFT 2
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#define PHY_DELAY 0x78
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#define PHY_CONFIG 0x80
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#define PHY_ADR 0x7c
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#define PHY_READ 0x7e
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#define CARRIER_SENSE_COUNTER 0x79 //byte
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#define SECURITY 0x5f //1209 this is sth wrong
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#define SECURITY_WEP_TX_ENABLE_SHIFT 1
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#define SECURITY_WEP_RX_ENABLE_SHIFT 0
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@ -214,44 +169,16 @@
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* RealTek names are used.
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*/
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#define IDR0 0x0000
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#define IDR1 0x0001
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#define IDR2 0x0002
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#define IDR3 0x0003
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#define IDR4 0x0004
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#define IDR5 0x0005
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/* 0x0006 - 0x0007 - reserved */
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#define MAR0 0x0008
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#define MAR1 0x0009
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#define MAR2 0x000A
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#define MAR3 0x000B
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#define MAR4 0x000C
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#define MAR5 0x000D
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#define MAR6 0x000E
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#define MAR7 0x000F
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/* 0x0010 - 0x0017 - reserved */
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#define TSFTR 0x0018
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#define TSFTR_END 0x001F
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#define TLPDA 0x0020
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#define TLPDA_END 0x0023
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#define TNPDA 0x0024
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#define TNPDA_END 0x0027
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#define THPDA 0x0028
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#define THPDA_END 0x002B
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#define BSSID 0x002E
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#define BSSID_END 0x0033
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#define CR 0x0037
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#define RF_SW_CONFIG 0x8 // store data which is transmitted to RF for driver
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#define RF_SW_CFG_SI BIT1
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#define PIFS 0x2C // PCF InterFrame Spacing Timer Setting.
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#define EIFS 0x2D // Extended InterFrame Space Timer, in unit of 4 us.
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#define BRSR 0x34 // Basic rate set
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@ -260,26 +187,16 @@
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#define ISR 0x003C
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#define TCR 0x0040
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#define TCR_END 0x0043
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#define RCR 0x0044
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#define RCR_END 0x0047
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#define TimerInt 0x0048
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#define TimerInt_END 0x004B
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#define TBDA 0x004C
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#define TBDA_END 0x004F
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#define CR9346 0x0050
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#define CONFIG0 0x0051
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#define CONFIG1 0x0052
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#define CONFIG2 0x0053
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#define ANA_PARM 0x0054
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#define ANA_PARM_END 0x0x0057
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#define MSR 0x0058
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#define CONFIG3 0x0059
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@ -294,37 +211,17 @@
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#define TESTR 0x005B
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/* 0x005C - 0x005D - reserved */
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#define PSR 0x005E
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/* 0x0060 - 0x006F - reserved */
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#define BcnItv 0x0070
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#define BcnItv_END 0x0071
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#define AtimWnd 0x0072
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#define AtimWnd_END 0x0073
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#define BintrItv 0x0074
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#define BintrItv_END 0x0075
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#define AtimtrItv 0x0076
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#define AtimtrItv_END 0x0077
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#define PhyDelay 0x0078
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#define CRCount 0x0079
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/* 0x007A - 0x007B - reserved */
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#define PhyAddr 0x007C
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#define PhyDataW 0x007D
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#define PhyDataR 0x007E
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#define PhyCFG 0x0080
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#define PhyCFG_END 0x0083
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/* following are for rtl8185 */
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#define RFPinsOutput 0x80
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#define RFPinsEnable 0x82
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@ -356,100 +253,13 @@
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#define MAX_RESP_RATE_SHIFT 4
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#define MIN_RESP_RATE_SHIFT 0
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#define RATE_FALLBACK 0xbe
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/*
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* 0x0084 - 0x00D3 is selected to page 1 when PSEn bit (bit0, PSR)
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* is set to 1
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*/
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#define Wakeup0 0x0084
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#define Wakeup0_END 0x008B
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#define Wakeup1 0x008C
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#define Wakeup1_END 0x0093
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#define Wakeup2LD 0x0094
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#define Wakeup2LD_END 0x009B
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#define Wakeup2HD 0x009C
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#define Wakeup2HD_END 0x00A3
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#define Wakeup3LD 0x00A4
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#define Wakeup3LD_END 0x00AB
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#define Wakeup3HD 0x00AC
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#define Wakeup3HD_END 0x00B3
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#define Wakeup4LD 0x00B4
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#define Wakeup4LD_END 0x00BB
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#define Wakeup4HD 0x00BC
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#define Wakeup4HD_END 0x00C3
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#define CRC0 0x00C4
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#define CRC0_END 0x00C5
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#define CRC1 0x00C6
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#define CRC1_END 0x00C7
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#define CRC2 0x00C8
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#define CRC2_END 0x00C9
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#define CRC3 0x00CA
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#define CRC3_END 0x00CB
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#define CRC4 0x00CC
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#define CRC4_END 0x00CD
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/* 0x00CE - 0x00D3 - reserved */
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/*
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* 0x0084 - 0x00D3 is selected to page 0 when PSEn bit (bit0, PSR)
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* is set to 0
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*/
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/* 0x0084 - 0x008F - reserved */
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#define DK0 0x0090
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#define DK0_END 0x009F
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#define DK1 0x00A0
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#define DK1_END 0x00AF
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#define DK2 0x00B0
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#define DK2_END 0x00BF
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#define DK3 0x00C0
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#define DK3_END 0x00CF
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/* 0x00D0 - 0x00D3 - reserved */
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/* 0x00D4 - 0x00D7 - reserved */
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#define CONFIG5 0x00D8
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#define TPPoll 0x00D9
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/* 0x00DA - 0x00DB - reserved */
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#define PHYPR 0xDA //0xDA - 0x0B PHY Parameter Register.
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#define CWR 0x00DC
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#define CWR_END 0x00DD
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#define RetryCTR 0x00DE
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/* 0x00DF - 0x00E3 - reserved */
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#define RDSAR 0x00E4
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#define RDSAR_END 0x00E7
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/* 0x00E8 - 0x00EF - reserved */
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#define LED_CONTROL 0xED
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#define FER 0x00F0
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#define FER_END 0x00F3
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#define FEMR 0x1D4 // Function Event Mask register
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#define FPSR 0x00F8
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#define FPSR_END 0x00FB
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#define FFER 0x00FC
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#define FFER_END 0x00FF
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@ -598,53 +408,10 @@
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#define CR9346_EED1 ((1<<1))
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#define CR9346_EED0 ((1<<0))
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#define CONFIG0_WEP104 ((1<<6))
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#define CONFIG0_LEDGPO_En ((1<<4))
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#define CONFIG0_Aux_Status ((1<<3))
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#define CONFIG0_GL ((1<<1)|(1<<0))
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#define CONFIG0_GL1 ((1<<1))
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#define CONFIG0_GL0 ((1<<0))
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#define CONFIG1_LEDS ((1<<7)|(1<<6))
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#define CONFIG1_LEDS1 ((1<<7))
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#define CONFIG1_LEDS0 ((1<<6))
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#define CONFIG1_LWACT ((1<<4))
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#define CONFIG1_MEMMAP ((1<<3))
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#define CONFIG1_IOMAP ((1<<2))
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#define CONFIG1_VPD ((1<<1))
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#define CONFIG1_PMEn ((1<<0))
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#define CONFIG2_LCK ((1<<7))
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#define CONFIG2_ANT ((1<<6))
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#define CONFIG2_DPS ((1<<3))
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#define CONFIG2_PAPE_sign ((1<<2))
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#define CONFIG2_PAPE_time ((1<<1)|(1<<0))
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#define CONFIG2_PAPE_time1 ((1<<1))
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#define CONFIG2_PAPE_time0 ((1<<0))
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#define CONFIG3_GNTSel ((1<<7))
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#define CONFIG3_PARM_En ((1<<6))
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#define CONFIG3_Magic ((1<<5))
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#define CONFIG3_CardB_En ((1<<3))
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#define CONFIG3_CLKRUN_En ((1<<2))
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#define CONFIG3_FuncRegEn ((1<<1))
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#define CONFIG3_FBtbEn ((1<<0))
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#define CONFIG4_VCOPDN ((1<<7))
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#define CONFIG4_PWROFF ((1<<6))
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#define CONFIG4_PWRMGT ((1<<5))
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#define CONFIG4_LWPME ((1<<4))
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#define CONFIG4_LWPTN ((1<<2))
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#define CONFIG4_RFTYPE ((1<<1)|(1<<0))
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#define CONFIG4_RFTYPE1 ((1<<1))
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#define CONFIG4_RFTYPE0 ((1<<0))
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#define CONFIG5_TX_FIFO_OK ((1<<7))
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#define CONFIG5_RX_FIFO_OK ((1<<6))
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#define CONFIG5_CALON ((1<<5))
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#define CONFIG5_EACPI ((1<<2))
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#define CONFIG5_LANWake ((1<<1))
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#define CONFIG5_PME_STS ((1<<0))
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#define MSR_LINK_MASK ((1<<2)|(1<<3))
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#define MSR_LINK_MANAGED 2
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@ -653,50 +420,16 @@
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#define MSR_LINK_ADHOC 1
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#define MSR_LINK_MASTER 3
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#define PSR_GPO ((1<<7))
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#define PSR_GPI ((1<<6))
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#define PSR_LEDGPO1 ((1<<5))
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#define PSR_LEDGPO0 ((1<<4))
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#define PSR_UWF ((1<<1))
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#define PSR_PSEn ((1<<0))
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#define SCR_KM ((1<<5)|(1<<4))
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#define SCR_KM1 ((1<<5))
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#define SCR_KM0 ((1<<4))
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#define SCR_TXSECON ((1<<1))
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#define SCR_RXSECON ((1<<0))
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#define BcnItv_BcnItv (0x01FF)
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#define AtimWnd_AtimWnd (0x01FF)
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#define BintrItv_BintrItv (0x01FF)
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#define AtimtrItv_AtimtrItv (0x01FF)
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#define PhyDelay_PhyDelay ((1<<2)|(1<<1)|(1<<0))
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#define TPPoll_BQ ((1<<7))
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#define TPPoll_HPQ ((1<<6))
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#define TPPoll_NPQ ((1<<5))
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#define TPPoll_LPQ ((1<<4))
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#define TPPoll_SBQ ((1<<3))
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#define TPPoll_SHPQ ((1<<2))
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#define TPPoll_SNPQ ((1<<1))
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#define TPPoll_SLPQ ((1<<0))
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#define CWR_CW (0x01FF)
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#define FER_INTR ((1<<15))
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#define FER_GWAKE ((1<< 4))
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#define FEMR_INTR ((1<<15))
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#define FEMR_WKUP ((1<<14))
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#define FEMR_GWAKE ((1<< 4))
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#define FPSR_INTR ((1<<15))
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#define FPSR_GWAKE ((1<< 4))
|
||||
|
||||
#define FFER_INTR ((1<<15))
|
||||
#define FFER_GWAKE ((1<< 4))
|
||||
|
||||
|
|
@ -716,17 +449,6 @@
|
|||
#define RCR_MXDMA_OFFSET 8
|
||||
#define RCR_FIFO_OFFSET 13
|
||||
|
||||
#define TMGDS 0x0C // Tx Management Descriptor Address
|
||||
#define TBKDS 0x10 // Tx AC_BK Descriptor Address
|
||||
#define TBEDS 0x14 // Tx AC_BE Descriptor Address
|
||||
#define TLPDS 0x20 // Tx AC_VI Descriptor Address
|
||||
#define TNPDS 0x24 // Tx AC_VO Descriptor Address
|
||||
#define THPDS 0x28 // Tx Hign Priority Descriptor Address
|
||||
|
||||
#define TBDS 0x4c // Beacon descriptor queue start address
|
||||
|
||||
#define RDSA 0xE4 // Receive descriptor queue start address
|
||||
|
||||
#define AckTimeOutReg 0x79 // ACK timeout register, in unit of 4 us.
|
||||
|
||||
#define RFTiming 0x8C
|
||||
|
|
@ -740,8 +462,6 @@
|
|||
|
||||
#define ACM_CONTROL 0x00BF // ACM Control Registe
|
||||
|
||||
#define RTL8185B_VER_REG 0xE1
|
||||
|
||||
#define IntMig 0xE2 // Interrupt Migration (0xE2 ~ 0xE3)
|
||||
|
||||
#define TID_AC_MAP 0xE8 // TID to AC Mapping Register
|
||||
|
|
@ -753,9 +473,7 @@
|
|||
#define AC_BE_PARAM 0xF8 // AC_BE Parameters Record
|
||||
#define AC_BK_PARAM 0xFC // AC_BK Parameters Record
|
||||
|
||||
#define BcnTimingAdjust 0x16A // Beacon Timing Adjust Register.
|
||||
#define GPIOCtrl 0x16B // GPIO Control Register.
|
||||
#define PSByGC 0x180 // 0x180 - 0x183 Power Saving by Gated Clock.
|
||||
#define ARFR 0x1E0 // Auto Rate Fallback Register (0x1e0 ~ 0x1e2)
|
||||
|
||||
#define RFSW_CTRL 0x272 // 0x272-0x273.
|
||||
|
|
@ -767,28 +485,11 @@
|
|||
#define PI_DATA_READ 0X360 // 0x360 - 0x361 Parallel Interface Data Register.
|
||||
#define SI_DATA_READ 0x362 // 0x362 - 0x363 Serial Interface Data Register.
|
||||
|
||||
//----------------------------------------------------------------------------
|
||||
// 8185B TPPoll bits (offset 0xd9, 1 byte)
|
||||
//----------------------------------------------------------------------------
|
||||
#define TPPOLL_BQ (0x01 << 7)
|
||||
#define TPPOLL_HPQ (0x01 << 6)
|
||||
#define TPPOLL_AC_VOQ (0x01 << 5)
|
||||
#define TPPOLL_AC_VIQ (0x01 << 4)
|
||||
#define TPPOLL_AC_BEQ (0x01 << 3)
|
||||
#define TPPOLL_AC_BKQ (0x01 << 2)
|
||||
#define TPPOLL_AC_MGQ (0x01 << 1)
|
||||
|
||||
//----------------------------------------------------------------------------
|
||||
// 8185B TPPollStop bits (offset 0x93, 1 byte)
|
||||
//----------------------------------------------------------------------------
|
||||
#define TPPOLLSTOP_BQ (0x01 << 7)
|
||||
#define TPPOLLSTOP_HPQ (0x01 << 6)
|
||||
#define TPPOLLSTOP_AC_VOQ (0x01 << 5)
|
||||
#define TPPOLLSTOP_AC_VIQ (0x01 << 4)
|
||||
#define TPPOLLSTOP_AC_BEQ (0x01 << 3)
|
||||
#define TPPOLLSTOP_AC_BKQ (0x01 << 2)
|
||||
#define TPPOLLSTOP_AC_MGQ (0x01 << 1)
|
||||
|
||||
|
||||
#define MSR_LINK_ENEDCA (1<<4)
|
||||
|
||||
|
|
@ -807,7 +508,6 @@
|
|||
#define VIQ_ACM_EN (0x01 << 6) //BIT6
|
||||
#define BEQ_ACM_EN (0x01 << 5) //BIT5
|
||||
#define ACM_HW_EN (0x01 << 4) //BIT4
|
||||
#define TXOPSEL (0x01 << 3) //BIT3
|
||||
#define VOQ_ACM_CTL (0x01 << 2) //BIT2 // Set to 1 when AC_VO used time reaches or exceeds the admitted time
|
||||
#define VIQ_ACM_CTL (0x01 << 1) //BIT1 // Set to 1 when AC_VI used time reaches or exceeds the admitted time
|
||||
#define BEQ_ACM_CTL (0x01 << 0) //BIT0 // Set to 1 when AC_BE used time reaches or exceeds the admitted time
|
||||
|
|
@ -838,7 +538,6 @@
|
|||
#define RTL8225z2_ANAPARAM_OFF 0x55480658
|
||||
#define RTL8225z2_ANAPARAM2_OFF 0x72003f70
|
||||
//by amy for power save
|
||||
#define RF_CHANGE_BY_SW BIT31
|
||||
#define RF_CHANGE_BY_HW BIT30
|
||||
#define RF_CHANGE_BY_PS BIT29
|
||||
#define RF_CHANGE_BY_IPS BIT28
|
||||
|
|
@ -856,18 +555,15 @@
|
|||
//{by amy 080312
|
||||
//0x7C, 0x7D Crystal calibration and Tx Power tracking mechanism. Added by Roger. 2007.12.10.
|
||||
#define EEPROM_RSV 0x7C
|
||||
#define EEPROM_XTAL_CAL_MASK 0x00FF // 0x7C[7:0], Crystal calibration mask.
|
||||
#define EEPROM_XTAL_CAL_XOUT_MASK 0x0F // 0x7C[3:0], Crystal calibration for Xout.
|
||||
#define EEPROM_XTAL_CAL_XIN_MASK 0xF0 // 0x7C[7:4], Crystal calibration for Xin.
|
||||
#define EEPROM_THERMAL_METER_MASK 0x0F00 // 0x7D[3:0], Thermal meter reference level.
|
||||
#define EEPROM_XTAL_CAL_ENABLE 0x1000 // 0x7D[4], Crystal calibration enabled/disabled BIT.
|
||||
#define EEPROM_THERMAL_METER_ENABLE 0x2000 // 0x7D[5], Thermal meter enabled/disabled BIT.
|
||||
#define EEPROM_CID_RSVD1 0x3F
|
||||
#define EN_LPF_CAL 0x238 // Enable LPF Calibration.
|
||||
#define PWR_METER_EN BIT1
|
||||
// <RJ_TODO_8185B> where are false alarm counters in 8185B?
|
||||
#define CCK_FALSE_ALARM 0xD0
|
||||
#define OFDM_FALSE_ALARM 0xD2
|
||||
//by amy 080312}
|
||||
|
||||
//YJ,add for Country IE, 080630
|
||||
|
|
|
|||
Loading…
Reference in a new issue