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Blackfin arch: fix bug - The SPORT_HYS bit is not set for BF561 0.5
IMHO the setting should depend on ANOMALY_05000305 which is about the availability of the bit, not ANOMALY_05000265 which only describes the SPORT sensitivity to noise (checked for BF561 only, though). If that's not true for other BF variants, maybe the definition of ANOMALY_05000265 for BF561 should be changed to '(1)' instead. Signed-off-by: Enrik Berkhan <Enrik.Berkhan@ge.com> Signed-off-by: Mike Frysinger <vapier.adi@gmail.com> Signed-off-by: Bryan Wu <cooloney@kernel.org>
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@ -17,7 +17,7 @@
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#define SDGCTL_WIDTH (1 << 31) /* SDRAM external data path width */
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#define PLL_CTL_VAL \
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(((CONFIG_VCO_MULT & 63) << 9) | CLKIN_HALF | \
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(PLL_BYPASS << 8) | (ANOMALY_05000265 ? 0x8000 : 0))
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(PLL_BYPASS << 8) | (ANOMALY_05000305 ? 0 : 0x8000))
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__attribute__((l1_text))
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static void do_sync(void)
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